Microelectronics, BSc course Field effect transistors 2: The MOSFETs http://www.eet.bme.hu/~poppe/miel/en/12-MOSFET1.pptx

The abstraction level of our study: SYSTEM + MODULE GATE Vout Vin CIRCUIT DEVICE n+ S D G 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014 2

Field effect transistors 1 FET = Field Effect Transistor – the flow of charge carriers is influenced by electric field transversal field is used to control Flow Channel depletion layer JUNCTION FET: depletion layers of pn-junctions close the channel Most important parameter: U0 pinch-off voltage Unipolar device: current is conducted by majority carriers Power needed for controlling the device  0 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Field effect transistors 2 MOSFET: Metal-Oxide-Semiconductor FET Most frequently used today oxide oxide - depletion layer + inversion layer Bulk Bulk First type: depletion mode device Second type: enhancement mode device Most important parameter: U0 pinch off voltage Most important parameter: VT threshold voltage 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Field effect transistors 3 Symbols: p channel n channel n channel enhancement mode p channel enhancement mode depletion mode n channel enhancement mode p channel n channel depletion mode p channel depletion mode 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

MOSFETs More realistic cross-sectional view of enhnacement mode MOSFETs: Gate oxide n+ Source Drain p substrate Bulk contact p+ stopper Field-Oxide (SiO2) Polysilicon Gate 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The most modern MOSFETs: 2007/2008 … Intel: 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

How is it manufactured? 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Metal gate MOS transistor In-depth structure: requires accurate mask alignment Source doping Gate Drain doping Thin oxide Layout view: Source Problems: metal gate – large VT Drain contact 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Poly-Si gate MOS transistor In-depth structure: self alignment Source doping Gate Drain doping thin oxide Layout view: Source Advantages smaller VT Drain contact 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

A poli-Si gate nMOS process Start with: p type substrate (Si wafer) cleaing, grow thick SiO2 – this is called field oxide 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The poli-Si gate nMOS process Create the active zone with photolithography coat with resist, expose to UV light through a mask, development, removal of exposed resists etching of SiO2 removal of the resist M1: active zone 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The poli-Si gate nMOS process Create the gate structure: growth of thin oxide deposit poly-Si pattern poly-Si with photolithography develop) exposure, (resist, etch poly-Si, etch thin oxide M2: poly-Si pattern 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The poli-Si gate nMOS process S/D doping (implantation) the exide (thin, thick) masks the dopants this way the self-alignment of the gate is assured Passivation: deposit PSG 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The poli-Si gate nMOS process Open contact windows through PSG photolithography (resist, expose pattern, develop) etching (copy the pattern) cleaning M3: contact window pattern 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The poli-Si gate nMOS process Metallization Deposit Al photolithography, etching, cleaning M4: metallization pattern The recepy of the process is given, the in-depth structure is determined by the sequence of the masks One needs to specify the shapes on the masks The set of shapes on subsequent masks is called layout 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Poli-Si gate self-aligned device PSG Structure: Source/drain doping thin oxide poli-Si gate metallization, contact window Layout: W L 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Steps of the self-aligned poli-Si gate process 1) Open window for the active region M photolitography, field oxide etching 2) Growth of thin oxide 3) Window for hidden contacts M Contacts the poli-Si gate (yet to be deposited) with the active region (after doping). 3) Deposit poli-Si 4) Patterning of poli-Si M 5) Open window through the thin oxide (etching only) 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Steps of the self-aligned poli-Si gate process 6) n+ doping: Form source and drain regions as well as wiring by diffusion lines. Through the hidden contact poli-Si gate will also be connected to diffused lines. 7) Deposit phosphor-silica glass (PSG) as insulator 8) Open contact windows through PSG-n M 9) Metallization 10) Patterning metallization layer M 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Layout of a depletion mode inverter Layout == set of 2D shapes on subsequent masks Masks are color coded: active zone: red poly-Si: green contact windows: black metal: blue Mask == layout layer S G D Where is a transistor? Channel between two doped regions: CHANNEL = ACTIVE AND POLY 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Further topics: Overview of operation of MOS transistors Characteristics Secondary effects Models 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Operation of MOSFETs The simplest (logic) model: open (off) / short (on) Gate Source (of carriers) Drain | VGS | | VGS | < | VT | | VGS | > | VT | Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) Ron enhancement mode device open short 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Operation of MOSFETs n-channel device: p-channel device: electrons are flowing p-channel device: holes are flowing same operation, change of the signs Normally OFF device: at 0 gate (control) voltage the are "open" (enhancement mode device) Normally ON device: at 0 gate (control) voltage the are "short" (depletion mode device) 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Overview of MOSFET types 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Overview of the operation The operation is based on the so called MOS capacitance: As a result of electrical field perpendicular to the gate surface positive charges accumulate at the metal (gate) in the p-type semiconductor first the positive charges are "swept" out and a depletion layer is formed further increasing the electric field, negative carriers are collected from the bulk under the metal if the voltage at the surface exceeds a threshold value, the type of the semiconducter gets "inverted": an inversion layer is formed VT threshold voltage – the minimal voltage needed to form the inversion layer; depends on: the energy levels of the semiconductor material the thickness and the dielectric constant of the oxide (SiO2) the doping level and dielectric constant of the semiconductor (Si) 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Overview of the operation Surface phenomena in case of the MOS capacitance Accumulation Depletion Inversion Strong inversion: UF = 2 F 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The MOS transistor MOS capacitance completed by two electrodes at its two sides: n-channel device: current conducted by electrons p-channel device: current conducted by holes 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Qualitative operation of the MOSFET If VGS > VT, inversion layer is formed the n+ region at the source can inject electrons into the inversion channel the positive potential at the drain induces flow of electrons in the channel, the positive potential of the drain reverse biases the pn junction formed there the electrons drifted there are all sank in the n+ region and the circuit is closed 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Qualitative operation of the MOSFET the charge density in channel depends on the VGS voltage there is a voltage drop in the channel, thus, the thickness of the inversion layer will deminish along the channel at a given VDSsat saturation voltage the thickness will reach 0, this is the so called pinch-off VDSsat = VGS - VT After this voltage is reached, the MOSFET operates in saturation mode, the drain voltage does not influence the drain current any longer. 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Qualitative operation of the MOSFET In the pinch-off region the charge transport takes place by means of diffusion current. 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

I-V charactersitics output charactersitic: ID=f(UDS), parameter: UGS input characteristc: ID=f(UGS) Output characteristic: In saturation: current constant The circuit designer can change the geometry only: the W width and the L length 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Example Calculate the saturation current of a MOSFET for UGS=5V if VT =1V, and the geometry a) W= 5μm, L=0.4μm , b) W= 0.8μm, L=5μm ! a) By changing the W/L ratio the drain current can be changed by orders of magnitude b) 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

I-V charactersitics VGS = 2.5V VDSsat = VGS - VT Quadratic dependece X 10-4 VGS = 2.5V VDSsat = VGS - VT Quadratic dependece Voltage controlled current source voltage controlled resistor VGS = 2.0V linear saturation ID (A) VGS = 1.5V VGS = 1.0V cut-off VDS (V) nMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Overview of the physics: Charges and potentials at the surface The threshold voltage The charateristics Secondary effects 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Potentials of the MOS structure oxide semiconductor 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Potentials of the MOS structure 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The threshold voltage of the MOSFET Inversion 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The threshold voltage of the MOSFET 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The threshold voltage of the MOSFET Flat-band potential: FB F T V + = SB U 2 P Bulk constant: 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Problem Data of a MOSFET device: Na = 41015 /cm3, relative dielectric constant of Si 11,8, az oxidé 3.9, oxide thickness dox = 0,03 m, MS = 0,2 V, QSS is neglected. Calculate the Fermi potential, the oxide capacitance, the bulk constant and the threshold voltage for USB = 0 V ! 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The charactersitics of an enhnacement mode MOSFET inversion layer Later we shall calculate these! triode region saturation 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Derivation of the charactersitic U(0) = UGS , U(L) = UGD inversion layer Qi(U) = Qi[U(x)] 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Derivation of the charactersitic inversion layer 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Derivation of the charactersitic inversion layer if if For all regions of operation! 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Saturation: UGD < VT The saturation region inversion layer For all regions of operation! Saturation: UGD < VT 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Overview of all types of MOSFETs 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Like an enhance mode MOSFET with a negative threshold voltage Depletion mode MOSFET Like an enhance mode MOSFET with a negative threshold voltage 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Capacitances of the MOSFET inversion layer Bulk S/D – B capacitance: reverse biased PN junction 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

The gate capacitance: x L Polysilicon gate Top view Gate-bulk overlap d L Polysilicon gate Top view Gate-bulk overlap Source n + Drain W t ox n + Cross section L Gate oxide 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Secondary effects Channel length reduction Narrow channel operation Temperature dependence Subthreshold current 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Dependence of threshold voltage on geometry Short channel: VT decreases Narrow channel: VT increases 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Velocity saturation Influences the operation of short channel devices (V/m) n (m/s) sat =105 Constant velocity constant mobility (slope = ) c= 5 Velocity saturation the speed of carriers (due to the collisions) becomes constant Normally, the velocity of the carriers is proportional to the electric field – carrier mobility is constant. However, at high field strengths, carriers fail to follow this linear model. For p-type silicon (nfets), the critical field at which electron saturation occurs is around 1.5 x10**6 V/m (1.5 V/um) and vsat ~ 10**5 m/s Holes in a n-type silicon saturate at the same velocity, although a higher electric field is needed to achieve velocity saturation. So velocity saturation effects are less pronounced in pfets. For a 0.25 micron NMOS device are only about 2 volts between the drain and source are needed to reach velocity saturation In a L = 0.25m channel device a few Volts of D-S voltage may already result in velocity saturation. 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Velocity saturation In short channel device velocity saturation takes place sooner (at lower voltage) ID Long channel devices Short channel devices VDSAT VGS-VT VGS = VDD VDS Normally, the velocity of the carriers is proportional to the electric field – carrier mobility is constant. However, at high field strengths, carriers fail to follow this linear model. For p-type silicon (nfets), the critical field at which electron saturation occurs is around 1.5 x10**6 V/m (1.5 V/um) and vsat ~ 10**5 m/s Holes in a n-type silicon saturate at the same velocity, although a higher electric field is needed to achieve velocity saturation. So velocity saturation effects are less pronounced in pfets. For a 0.25 micron NMOS device are only about 2 volts between the drain and source are needed to reach velocity saturation 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Short channel charactersitics ID (A) VDS (V) X 10-4 VGS = 1.0V VGS = 1.5V VGS = 2.0V VGS = 2.5V Linear dependence Early velocity saturation Linear Saturation nMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Temperature dependence 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Subthreshold current Assuming a given VT is rough model; in reality the current vanishes exponentially with the gate voltage: 10-2 linear region quadratic region ID (A) subthreshold, exponential region ID ~ IS e (qVGS/nkT) where n  1 VT 10-12 VGS (V) 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Subthreshold current Continuous transition between the ON and OFF states Subthreshold is undesired: strong deviation from the switch model I0, n – empirical parameters, n is typically 1.5 Slope factor: S = n (kT/q) ln (10) (tipically: 60 ..100 mV/decade) – the smaller the better, depends on. Can be reduced by SOI: SiO2 Si Si substrate e.g. SIMOX process 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Subthreshold ID(VGS) charactersitic VDS : 0 .. 0.5V 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Subthreshold ID(VDS) charactersitic VGS : 0 .. 0.3V 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

MOS transistor models Neded for circuit simulators (SPICE, TRANZ-TRAN, ELDO, SABER, stb) Different levels of complexity: level0, 1, 2, ...n, EKV, BSIM3, BSIM4 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Photograph by optical microscope Micro-photograph by SEM Examples for MOSFETs inversion layer Photograph by optical microscope S G D Micro-photograph by SEM 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Some more complex MOS circuits n- & p-channel devices : CMOS circuit, see later 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014

Some more complex MOS circuits Designed by CAD tools 05-11-2014 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008-2014