EE415 VLSI Design The Devices: Diode [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary deep-sub-micron effects Future trends

EE415 VLSI Design Outline l Motivation and Goals l Semiconductor Basics l Diode Structure l Operation »Static model –Depletion capacitance –Carrier density profiles l Diffusion capacitance »Dynamic response –Switching speed  next session l Spice model 

EE415 VLSI Design Semiconductor Basics  I l Electrons in intrinsic (pure) Silicon »covalently bonded to atoms »“juggled” between neighbors »thermally activated: density  e T »move around the lattice, if free »leave a positively charged `hole’ behind

EE415 VLSI Design Semiconductor Basics  II l Two types of intrinsic carriers »Electrons (n i ) and holes (p i ) »In an intrinsic (no doping) material, n i =p i »At 300K, n i =p i is low (10 10 cm -3 ) »Use doping to improve conductivity

EE415 VLSI Design Semiconductor Basics  III l Extrinsic carriers »Also two types of dopants (donors or acceptors) –Donors bring electron (n-type) and become  ive ions –Acceptors bring holes (p-type) and become  ive ions »Substantially higher densities (  cm -3 ) »Majority and minority carriers –if n>>p (n-type) electrons majority and holes minority –Random recombination and thermal generation

EE415 VLSI Design The Diode p n BA SiO 2 Al Cross section of pn-junction in an IC process P-type region doped with acceptor impurities (boron) N-type region doped with donor impurities (phosphorus, arsenic)

EE415 VLSI Design The Diode A B n p A B Al One-dimensional representationdiode symbol The pn region is assumed to be thin ( step or abrupt junction) Different concentrations of electrons (and holes) of the p and n - type regions cause a concentration gradient at the boundary Simplified structure

EE415 VLSI Design Concentration Gradient causes electrons to diffuse from n to p, and holes to diffuse from p to n This produces immobile ions in the vicinity of the boundary Region at the junction with the charged ions is called the depletion region or space-charge region Charges create electric field that attracts the minority carriers, causing them to drift Drift counteracts diffusion causing equilibrium ( I drift = -I diffusion ) Depletion Region

EE415 VLSI Design Depletion Region Zero bias conditions p more heavily doped than n (N A > N B ) Electric field gives rise to potential difference in the junction, known as the built-in potential

EE415 VLSI Design Built-in Potential Where  T is the thermal voltage n i is the intrinsic carrier concentration for pure Si (1.5 X cm -3 at 300K), so for

EE415 VLSI Design Forward Bias hole diffusion electron diffusion pn hole drift electron drift +- Applied potential lowers the potential barrier, I diffusion > I drift Mobile carriers drift through the dep. region into neutral regions become excess minority carriers and diffuse towards terminals Read about drift and diffusion currents at:

EE415 VLSI Design Forward Bias p n0 n p0 -W 1 W 2 0 p n ( W 2 ) n-regionp-region L p diffusion Typically avoided in Digital ICs x W n Metal contact to n-region -W p Metal contact to p-region p (x) n n (x) p minority carrier concentration

EE415 VLSI Design Reverse Bias hole diffusion electron diffusion pn hole drift electron drift -+ Applied potential increases the potential barrier Diffusion current is reduced Diode works in the reverse bias with a very small drift current

EE415 VLSI Design Reverse Bias x n p0 -W 1 W 2 0 n-region p-region p n0 diffusion The Dominant Operation Mode -W p Metal contact to p-region W n Metal contact to n-region n p0

EE415 VLSI Design Models for Manual Analysis Accurate Strongly non-linear Prevents fast DC bias calculations Conducting diode replaced by voltage source V Don =0.7V Good for first order approximation

EE415 VLSI Design Typical Diode Parameters V D I D =I S (e V D /  T – 1) + – D n =25 cm 2 /sec D p =10cm 2 /sec W n =5  m W p =0.7  m W 2 =0.15  m W 1 =0.03  m Geometry, doping and material constants lumped in Is Diffusion coefficient minority carrier concentration

EE415 VLSI Design Diode Current Ideal diode equation:

EE415 VLSI Design Depletion Capacitance l Due to depletion charges »V D changes space charge »Forms a capacitor C j –Charge modulated by voltage l Ideality factor (m) depends on junction gradient

EE415 VLSI Design Equivalent Capacitances  I l Linearize diode capacitances »C j is a non-linear function of V D –When bias changes then C j also changes –Hard to use in manual analyses »Instead use equivalent capacitance –Gives the same total charge for a given V D transition »Equivalent depletion capacitance –Must be worked out for a given V 1  V 2 transition

EE415 VLSI Design Equivalent Capacitances  II »Equivalent diffusion capacitance –Must be worked out for currents at given V 1  V 2 transition l C eq depends on process constants and {V 1,V 2 } »Example: –for A D =0.5  m 2 C j0 =2 fF/  m 2,  0 =0.64 V and m=0.5 l then K eq  and C eq  1.24 fF/  m 2 if switched between 0 and -2.5 V l So unit capacitance C j  0.9 fF/  m 2 or C j  0.45 fF for the total diode area

EE415 VLSI Design Secondary Effects: Breakdown l Cannot bear too large reverse biases »Drift field in depletion region will get extremely large »Minority carriers caught in this large field will get very energetic –Energetic carriers can knock atoms and create a new n-p pair –These carriers will get energetic, too, and so on: thus large currents! l Two types »Avalanche breakdown –Above mechanism »Zener breakdown –More complicated l Can damage diode

EE415 VLSI Design Diode SPICE Model l Required for circuit simulations »Must capture important characteristics but also remain efficient »Extra parameter in the model: n (emission coefficient, 1  n  2) –Fixes non-ideal behavior due to broken assumptions l Additional series resistance accounts for body+contact l Nonlinear capacitance includes both C D and C j

EE415 VLSI Design SPICE Parameters l Often supplied by the fab to the designer »If not must be measured and fit the parameters l Assumes default values, if not explicitly defined l Pay attention to the units and spelling