Bill W. Haynes Slide 1 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Common Design for Multiple Timing Applications u Available PLD Based SERDES Devices u Time to Digital Converter (TDC) w/ PLD Based SERDES u Timing Distribution System (TDS) w/ PLD Based SERDES u Other PLD Based SERDES Potential Applications u Simulation Results of TDC w/ 400ps Resolution u Prototype TDC/TDS Card Status Simulation Only

Bill W. Haynes Slide 2 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Available PLD Based SERDES Devices u Cypress Programmable Serial Interface (PSI) u CPLD w/ a single channel 2.5Gbs SERDES device u Cost ~ $140 u CPLD w/ a quad channel 1.5Gbs SERDES device u Cost ~ $200 u Both devices in production u Xilinx-II Pro FPGA u Up to 16-channel FPGA w/ Gbs SERDES devices u Not in production & Cost is UNK u Altera Stratix FPGA u Up to 80-channel FPGA w/ 800 Mbs SERDES devices u Not in production & Cost is UNK

Bill W. Haynes Slide 3 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u High-Resolution TDC Block Diagram Detector Output (CML) 156 MHz Ref Clk Serdes Control 16bit Data FPGA/CPLD ( Cypress / Xilinx ) Serial Receiver (Cypress / Xilinx) General I/O

Bill W. Haynes Slide 4 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Programmable TDC Features u Resolution of 400ps (or better) is possible u Single channel Cypress PSI w/ 2.5 Gbs SERDES (in production) u Multiple channel FPGAs planned by several vendors u Single & Multiple channel dedicated SERDES u Available or Planned by several vendors u 8 channel TDC at lower resolution (666 ps) u 4-channel Cypress device (in production) u 8-channel Cypress device (planned) u 80 channels at lower resolution (1.25 ns) u Altera Stratix FPGA u Not in production u Fully Programmable (VHDL) Backend u Timing compensation u Interface to external world (PCI, CPCI, etc.) u Transmit TDC data over one of the serial links

Bill W. Haynes Slide 5 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDC w/ 400ps Resolution u Input Pulse Width = FFFF F > 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns u Reference Counter Time = T Ref = 105.6ns u T Ref Offset = # of 0 bits from T Ref x 400ps = 0 x 400ps = 0ps u Input Prop. Delay = ns + T Ref Offset = ns 105.6ns FFFF

Bill W. Haynes Slide 6 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDC w/ 400ps Resolution u Input Pulse Width = 7FFF FC > 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns u Reference Counter Time = T Ref = 105.6ns u T Ref Offset = # of 0 bits from T Ref x 400ps = 1 x 400ps = 400ps u Input Prop. Delay = ns + T Ref Offset = ns +400ps = 7FFF ns 105.6ns

Bill W. Haynes Slide 7 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDC w/ 400ps Resolution u Input Pulse Width = 3FFF FE > 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns u Reference Counter Time = T Ref = 105.6ns u T Ref Offset = # of 0 bits from T Ref x 400ps = 2 x 400ps = 800ps u Input Prop. Delay = ns + T Ref Offset = ns +800ps = 3FFF ns 105.6ns

Bill W. Haynes Slide 8 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDC w/ 400ps Resolution u Input Pulse Width = 0FFF FF > 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns u Reference Counter Time = T Ref = 105.6ns u T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps u Input Prop. Delay = ns + T Ref Offset = ns +1600ps = 0FFF ns 105.6ns

Bill W. Haynes Slide 9 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDC w/ 400ps Resolution u Input Pulse Width = 0001 FFFF F000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns u Reference Counter Time = T Ref = 105.6ns u T Ref Offset = # of 0 bits from T Ref x 400ps = 15 x 400ps = 6000ps u Input Prop. Delay = ns + T Ref Offset = ns +6000ps = ns 105.6ns

Bill W. Haynes Slide 10 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDC w/ 400ps Resolution u Input Pulse Width = 0000 FFFF F800-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns u Reference Counter Time = T Ref = 105.6ns + 6.4ns = ns u T Ref Offset = # of 0 bits from T Ref x 400ps = 0 x 400ps = 0ps u Input Prop. Delay = ns + T Ref Offset = ns +0ps = FFFF ns 112.0ns

Bill W. Haynes Slide 11 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDC w/ 400ps Resolution u Input Pulse Width = FFE 0000-> 11bits x 6.4ns/16 = 11 x 400ps = 4.4ns +/-200ps u Reference Counter Time = T Ref = 105.6ns + 0ns = ns u T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps u Input Prop. Delay = ns + T Ref Offset = ns +1600ps = 0FFE ns 105.6ns

Bill W. Haynes Slide 12 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDC w/ 400ps Resolution u Input Pulse Width = E > 3bits x 6.4ns/16 = 3 x 400ps = 1.2ns +/-200ps u Reference Counter Time = T Ref = 105.6ns + 0ns = ns u T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps u Input Prop. Delay = ns + T Ref Offset = ns +1600ps = 0E ns 105.6ns 1.0ns

Bill W. Haynes Slide 13 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDC w/ 400ps Resolution u Input Pulse Width = > 1bits x 6.4ns/16 = 1 x 400ps = 400ps +/-200ps u Reference Counter Time = T Ref = 105.6ns + 0ns = ns u T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps u Input Prop. Delay = ns + T Ref Offset = ns +1600ps = ns 105.6ns 400ps

Bill W. Haynes Slide 14 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Prototype TDC/TDS Card Status u 4 –PCI Card w/ a 1.5Gbs Resolution TDC/TDS u Design near completion u PC board layout will start in March u Prototype Testing in May/June u Beam Testing in November Test Beam

Bill W. Haynes Slide 15 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Timing (or Clock) Distribution System (TDS) u Discussed at the CKM Ann Arbor Workshop u Uses a 2-channel 2.5 Gbs Cypress device u Can be converted to a high resolution TDC by: u Setting lock to reference rather than lock to data

Bill W. Haynes Slide 16 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Timing (or Clock) Distribution System (TDS) u The Far-End of the Cable is a Common Reference for all Receivers u Reference can be Determined by: T = (Round Trip Time)/2 Or u The Time from Incident Wave to the Reflected Wave Divided by Two I- Wave R- Wave Round Trip Time = 2T I- Wave R- Wave T farEnd = (T I-Wave – T R-Wave )/2 I- Wave R- Wave T farEnd = (T I-Wave – T R-Wave )/2

Bill W. Haynes Slide 17 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u TDS Simpified Block Diagram

Bill W. Haynes Slide 18 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Other PLD Based SERDES Potential Applications u Data Links for DAQ u Control & Monitoring Links

Bill W. Haynes Slide 19 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u PCI Test Adapter (PTA)

Bill W. Haynes Slide 20 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Cypress CPLD