Confidential and Proprietary Information DDR333 – The New Wave Bill Gervasi Technology Analyst, Transmeta Corporation Chairman, JEDEC Memory Parametrics

Confidential and Proprietary Information RAM Evolution Mainstream Memories Simple, incremental steps “DDR I” “DDR II” 1100MB/s PC133 DDR MB/s DDR MB/s DDR MB/s 1600MB/s DDR200 “SDR”

Confidential and Proprietary Information Key to System Evolution Never over-design! Implement just enough new features to achieve incremental improvements Use low cost high volume infrastructure –Processes –Packages –Printed circuit boards

Confidential and Proprietary Information New DDR Specifications DDR Components & Modules –DDR333 chips –PC2700 MicroDIMM –PC2700 SO-DIMM –PC2700 Registered DIMM –PC2700 Unbuffered DIMM DDR Component Packaging –66 pin TSOP-II –60 ball FBGA

Confidential and Proprietary Information DDR MHz data rate per pin Approved for both TSOP and FBGA –First introduction of FBGA into SDRAM family –One package-dependent timing consideration Most improvements from tighter DLL design –Purpose of the DLL is accurate delivery of data and strobes during read cycles

Confidential and Proprietary Information Achieving 333 Mbps Data Rate

Confidential and Proprietary Information DLL Effects Clock jitter, pulse width distortion, DQS pull in or push out from pattern effects, p-channel to n-channel variation CK tDQSCK * CK DQS DDR266 = 750 ps DDR333 = 600 ps

Confidential and Proprietary Information Data Capture Parameters Data pin skew, simultaneous switching output effects, output driver variation Note that data valid window width is package independent! tQHS * (simplified view) DQS DDR266 = 750 ps DDR333 = 550 ps for TSOP = 500 ps for FBGA DDR266 = 750 ps DDR333 = 450 ps for TSOP = 400 ps for FBGA tDQSQ * data

Confidential and Proprietary Information Managing Power

Confidential and Proprietary Information Power = CV 2 f% Factors: Capacitance (C) Voltage (V) Frequency (f) Duty cycle (%) Power states Keys to low power design: Reduce C and V Match f to demand Minimize duty cycle Utilize power states

Confidential and Proprietary Information 2.5V Signaling = Power Savings 2.5V 1.60V 0.90V 1.43V 1.07V 1.25V VSS VDDQ VREF VIHac VIHdc VILdc VILac PC V DDR V

Confidential and Proprietary Information Package Capacitance (pF) Reduced capacitance lowers power, makes design easier Input Capacitance Input/Output Capacitance MinMaxDelta Input Capacitance Input/Output Capacitance TSOP-II Package FBGA Package Approximate 10-25% reduction

Confidential and Proprietary Information Serves Many Market Segments Servers, Workstations: –High bandwidth, high capacity –Registered DIMMs Desktop PCs, Network Routers: –Low latency –Unbuffered DIMMs and SO-DIMMs Mobile, Handheld: –Low power –SO-DIMMs and MicroDIMMs

Confidential and Proprietary Information Wide Spread Support DRAM suppliers –Infineon, Micron, Mitsubishi, Nanya, Samsung, and others Modules suppliers –ATP, Kentron, Kingston, Melco, Micron, PNY, Samsung, and others Users –ALi, AMD, Intel, SiS, Via, Transmeta, and others Rapid adoption throughout the industry has begun

Confidential and Proprietary Information Memory of choice for the future Simple transition from DDR266 Widespread adoption in all market segments

Confidential and Proprietary Information Thank You