Computer Science 210 Computer Organization The Instruction Execution Cycle

Program Development Compiler Linker Loader Runtime System Editor Translate to machine code Add library code Place code in appropriate memory locations Execute code Create source code

Runtime System: Execution Cycle Fetch Decode Execute Load instruction from memory Figure out what to do Do it Memory (array of instructions) This cycle repeats until a HALT instruction is reached

A Machine Language Instruction Specifies an opcode and one or more operands The control unit interprets the sequence of bits and sends a sequence of control signals to other units OpcodeOperand(s)

Example: LC-3 ADD Instruction Each instruction has a four-bit opcode in bits [15:12] This instruction also specifies two source registers and one destination register Add the contents of R2 and R6 and store the result in R6 Format: Code:

LDR (Load Data Relative) Instruction Sign-extend the Offset value to 16 bits, add it to the contents of the Base register, and load the datum at the resulting memory address into the Dst register Load the contents of memory at address (R3 + 6) into R2 Format: Code:

The LC-3 Instruction Set (page 119) 4 bits per opcode, 16 distinct opcodes But some instructions share an opcode Example: So, actually 20 distinct instructions ADD DR SR1 SR2, when bit 5 is clear ADD DR SR1 IR[4:0], when bit 5 is set

Types of Instructions Computation: ADD, AND, etc. Data movement: LDR, etc. Control: BR, JMP, JSR, etc. Complete set in Table 5.3, page 119 of text

Detailed View of Instruction Processing Fetch Decode Execute Fetch Decode Evaluate address Fetch operands Execute operation Store result

Instruction Processing: Fetch Fetch Decode Evaluate address Fetch operands Execute operation Store result Load next instruction into IR from memory at address in PC: Then increment address in PC MAR = PC Send read signal to memory IR = MDR

Instruction Processing: Decode Fetch Decode Evaluate address Fetch operands Execute operation Store result Identify the opcode: Depending on the opcode, identify the other operands from the remaining bits Bits [15:12] in LC-3 4-to-16 decoder asserts a control line For the first ADD, bits [11:9] = Destination register bits [8:6] = Source register 1 bits [2:0] = Source register 2

Instruction Processing: Evaluate Address Fetch Decode Evaluate address Fetch operands Execute operation Store result For instructions with memory access, compute the address used for access Add offset to base register Add offset to PC Add offset to zero Etc.

Instruction Processing: Fetch Operands Fetch Decode Evaluate address Fetch operands Execute operation Store result Obtain the operands needed for the operation Load data from memory (LDR) Read data from register file (ADD) Etc.

Fetch Decode Evaluate address Fetch operands Execute operation Store result Perform the operation using the operands Send operands to ALU and assert the ADD signal Do nothing (for LOAD and STORE) Etc. Instruction Processing: Execute Operation

Instruction Processing: Store Result Fetch Decode Evaluate address Fetch operands Execute operation Store result Write results to destination (register or memory): Write address to MAR Write data to MDR Assert write signal to memory To destination register (ADD, LDR) For STORE instruction,

Changing the Sequence of Instructions Fetch increments the PC by 1 Loops, if-statements, procedure calls don’t do this Control instructions modify the PC directly –Jumps: unconditional, always taken –Branches: conditional, depend on contents of status registers

The JMP Instruction Set the PC to the address contained in a register This register is specified in IR[8:6] Load the contents of R3 into the PC Format: Code:

The Control Unit The control unit is a finite state machine; a simplified view:

Stopping the Computer As long as the clock is running, the execution cycle continues If not processing instructions in your program, it’s processing instructions in the OS To stop: AND the generator signal with 0