Serial Peripheral Interface Module MTT M SERIAL PERIPHERAL INTERFACE (SPI)

Serial Peripheral Interface Module MTT M Module Objective Understand SPI format and data transfersgure the control registers Transmit and receive data Module exercise: Configure the SPI to transmit and receive characters to/from another device in Master mode at a 1 MHz rate

Serial Peripheral Interface Module MTT M SERIAL PERIPHERAL INTERFACE MODULE 68HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable ROM LVI COP Monitor ROM IRQ BREAK RESET Features of the SPI module include the following: Full-Duplex Operation Master and Slave Modes Separate Transmit and Receive Registers Four Master Mode Frequencies (Maximum = Bus Frequency  2) Maximum Slave Mode Frequency = Bus Frequency Separate Clock Ground for Reduced Radio Frequency (RF) Interference Serial Clock with Programmable Polarity and Phase Bus Contention Error Flag Overrun Error Flag Two Separately Enabled Interrupts with DMA or CPU Service: SPRF (SPI Receiver Full) SPTE (SPI Transmitter Empty) Programmable Wired-OR Mode I2C (Inter-Integrated Circuit) Compatibility

Serial Peripheral Interface Module MTT M SPI I/O Registers Three registers control and monitor SPI operations: SPI Control Register (SPCR) SPI Status and Control Register (SPSCR) SPI Data Register (SPDR)

Serial Peripheral Interface Module MTT M SPI Modes Master mode Only a master SPI initiates a transmission Data is shifted out via Master Out Slave In (MOSI) line Data is shifted in via Master In Slave Out (MISO) line Transmission ends after 8 cycles of serial clock (SPSCK) Slave Mode Transfer synchronized to serial clock (SPSCK) from Master Data is shifted in via the Master Out Slave In (MOSI) line Data is shifted out via the Master In Slave Out (MISO) line

Serial Peripheral Interface Module MTT M Slave Select Pin SS Shift Register MOSI MISO +5v SS MASTER SLAVE Baud Rate Gen. SPSCK Slave Select (SS) Master mode –SS held high during transmission –Acts as error detection input –Can be general purpose output Slave mode –SS must remain low until transmission completes 0 = Enables slave 1 = Disables slave

Serial Peripheral Interface Module MTT M SPI Control Register SPI Control Register (SPCR) SPI Master (SPMSTR) –Selects master mode or slave mode operation 1 = Master mode 0 = Slave mode SPI Master and Slave need identical clock polarity and phase settings Clock Polarity (CPOL) –Determines clock state when idle Clock Phase (CPHA) 1 = Begin capturing data on second clock cycle edge 0 = Begin capturing data on first clock cycle edge* – When CPHA = 0, the SS must be deasserted and reasserted between each transmitted byte RESET: WRITE: READ: SPRIEDMASSPMSTR CPOL CPHA SPWOMSPE SPTIE SPCR SPI Enable (SPE) 1 = SPI module enabled 0 = SPI module disabled Recommend disabling SPI before initializing or changing clock phase, clock polarity, or baud rate

Serial Peripheral Interface Module MTT M Clock Polarity and Phase SPI Control Register (SPCR) SPI modules need identical Clock polarity and phase CPHA CPOL MSBBit 6 Bit 5 Bit 4Bit 3Bit 2 Bit 1 LSB MOSI/MISO Capture Strobe SPSCK SS

Serial Peripheral Interface Module MTT M SPI Baud Rate SPI Status and Control Register (SPSCR) SPI rate select bits (SPR1, SPR0) –Sets the Master SPSCK clock frequency –No effect in the Slave devices – Baud Rate = CGMOUT / Baud Rate Divisor SPR1:SPR0 Divided By System Clock (System Clock Freq. = 8 MHz) Baud Rate MHz 1 MHz 250 KHz 62.5 KHz RESET: WRITE: READ:SPRF0 OVRFMODF SPTE SPR1SPR0 SPSCR 0

Serial Peripheral Interface Module MTT M SPI Data Register SPI Data Register (SPDR) Read/Write buffer for SPI data Write operation –Writes data to transmit data register Read operation –Reads data in receive data register RESET: UNAFFECTED BY RESET WRITE: READ: Bit 7Bit 6Bit 5 Bit 4Bit 3Bit 2 Bit 1 Bit 0 SPDR

Serial Peripheral Interface Module MTT M SPI Status Flags SPI Status and Control Register (SPSCR) SPI Receiver Receiver Full (SPRF) –Set when a byte is shifted from shift register to the receive data register –Cleared by reading SPSCR then reading SPDR 1 = Receive data register full 0 = Receive data register not full SPI Transmitter Empty (SPTE) –Set when a byte is transferred from SPDR to the shift register –Cleared by reading SPDR register 1 = Transmit data register empty 0 = Transmit data register not empty RESET: WRITE: READ:SPRF0 OVRFMODF SPTE SPR1SPR0 SPSCR 0

Serial Peripheral Interface Module MTT M SPI Interrupts SPI Control Register (SPCR) SPI Receiver Interrupt Enable Bit (SPRIE) –Interrupt generated when SPRF flag set SPI Transmit Interrupt Enable (SPTIE)) –Interrupt generated when SPTE flag set 1 = Interrupt enabled 0 = Interrupt disabled Direct Memory Access Select (DMAS) –Selects either DMA or CPU interrupt request –SPRIE/SPTIE bits still enable or disable interrupts RESET: WRITE: READ: SPRIEDMASSPMSTR CPOL CPHA SPWOMSPE SPTIE SPCR

Serial Peripheral Interface Module MTT M Initialization SPI Initialization sequence 1) Initialize SPI clock frequency ( SPR1 and SPR0 in SPSCR ) 2) Set clock configuration ( CPOL and CPHA bits in SPSCR ) 3) Select Master/Slave operation ( SPMSTR in SPCR ) 4) Enable interrupts if desired ( SPTIE, SPRIE in SPCR ) 5) Enable the SPI system ( SPE in SPCR ) Should enable Master before Slaves

Serial Peripheral Interface Module MTT M Master to Slave Transfer Simple Polled operation 1) Initialize the SPI 2) Select SS to Slave device (hardware dependent 3) Write byte to SPDR 4) Wait for SPI Transmitter Empty Flag (SPTE) 5) Read the SPDR 6) Release SS to Slave (hardware dependent)

Serial Peripheral Interface Module MTT M SPI Exercise Part 1: Initialize a SPI to the following: Master mode 1 MHz baud rate ( 8 MHz system clock ) Clock phase = 1 and clock polarity = 0 Polled operation Part 2: Write a procedure to transmit the character in the Accumulator to the Slave device. Then wait for the received character and place it into the Accumulator. (The Master SS is tied to V DD and the Slave SS is tied to ground)

Serial Peripheral Interface Module MTT M

Serial Peripheral Interface Module MTT M Additional Information Wired-Or Mode SPI Control Register (SPCR) SPI Wired OR Mode (SPWOM) –Configures MISO, MOSI, and SPSCK outputs to be open-drain drivers –Allows multiple-master systems –Provides some protection against CMOS latchup RESET: WRITE: READ: SPRIEDMASSPMSTR CPOL CPHA SPWOMSPE SPTIE SPCR

Serial Peripheral Interface Module MTT M Additional Information Overflow and Mode Fault Status Flags SPI Status and Control Register (SPSCR) Overflow flag (OVRF) –Failure to read data register before it is over written –Incoming data bytes are lost Data register contents unaffected –Cleared by reading the data register Mode Fault flag (MODF) –Master mode only –Indicates another master tried to access this device –Set when another device pulls SS pin low –Cleared by a write to the SPSCR RESET: WRITE: READ:SPRF0 OVRFMODF SPTE SPR1SPR0 SPSCR 0

Serial Peripheral Interface Module MTT M Additional Information Low Power Modes Low Power Modes WAIT –SPI mode remains active –SPI registers are not accessible Except by DMA –Enabled SPI interrupts will exit wait mode STOP –SPI module becomes inactive –No affect on register conditions –Operation continues after an external interrupt

Serial Peripheral Interface Module MTT M SPSCR WRITE: READ: Bit 7Bit 6Bit 5 Bit 4Bit 3Bit 2 Bit 1 Bit 0 SPDR SPRIE SPCR WRITE: READ: DMAS SPMSTR CPOL CPHA SPWOM SPESPTIE Register Summary SPR1SPR0 WRITE: READ: SPRF0OVRF MODFSPTE 0

Serial Peripheral Interface Module MTT M