Microelectronic Systems--University of Tennessee 1 1 Music Synthesizer Design Christopher Boyd Ki Shin Electrical & Computer Engineering University of.

Slides:



Advertisements
Similar presentations
Internal Logic Analyzer Final presentation-part B
Advertisements

Internal Logic Analyzer Final presentation-part A
Proximity Sensor Theremin Khoa Nguyen Walter Hudson Dennis Gilbert G. Hewage Thushara.
University Of Vaasa Telecommunications Engineering Automation Seminar Signal Generator By Tibebu Sime 13 th December 2011.
EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.
Sound Mixer. Sound Mixers: Overview Applications Some of the most common uses for sound mixers include: Music studios and live performances: Combining.
Stop Watch Sean Hicks Dongpu Jin ELEC 307 Project 2 Instructor: Alvaro Pinto April/12/2011.
1 Performed By: Khaskin Luba Einhorn Raziel Einhorn Raziel Instructor: Rivkin Ina Spring 2004 Spring 2004 Virtex II-Pro Dynamical Test Application Part.
1 Project supervised by: Dr Michael Gandelsman Project performed by: Roman Paleria, Avi Yona 12/5/2003 Multi-channel Data Acquisition System Mid-Term Presentation.
Spring 2002EECS150 - Lec13-proj Page 1 EECS150 - Digital Design Lecture 13 - Final Project Description March 7, 2002 John Wawrzynek.
Customizable Audio Kaleidoscope Agustya Mehta, Dennis Ramdass, Tony Hwang Final Project Spring 2007.
FPGA BASED IMAGE PROCESSING Texas A&M University / Prairie View A&M University Over the past few decades, the improvements from machine language to objected.
1 Project supervised by: Dr Michael Gandelsman Project performed by: Roman Paleria, Avi Yona 26/4/2004 Multi-channel Data Acquisition System Final_A Presentation.
Super Fast Camera System Performed by: Tokman Niv Levenbroun Guy Supervised by: Leonid Boudniak.
Implementation of DSP Algorithm on SoC. Characterization presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompany engineer : Emilia Burlak.
ECE 448: Spring 12 Lab 4 – Part 2 Finite State Machines Basys2 FPGA Board.
2 Outline Digital music The power of FPGA The “DigitalSynth” project –Hardware –Software Conclusion Demo.
Microelectronic Systems--University of Tennessee 1 1 Music Synthesizer Design Christopher Boyd Ki Shin Electrical & Computer Engineering University of.
Introduction to Counter in VHDL
Sub-Nyquist Sampling DSP & SCD Modules Presented by: Omer Kiselov, Daniel Primor Supervised by: Ina Rivkin, Moshe Mishali Winter 2010High Speed Digital.
Anthony Gaught Advisors: Dr. In Soo Ahn and Dr. Yufeng Lu Department of Electrical and Computer Engineering Bradley University, Peoria, Illinois May 7,
Song Pro Retro Alex Harper. Contents of Presentation Inspiration Basic Concept Speaker Module.sng file structure Song Pro Retro: Light Song Pro Retro:
ECE 545 Project 1 Part IV Key Scheduling Final Integration List of Deliverables.
Lecture #3 Page 1 ECE 4110– Sequential Logic Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.No Class Monday, Labor Day Holiday 2.HW#2 assigned.
1 Keyboard Controller Design By Tamas Kasza Digital System Design 2 (ECE 5572) Summer 2003 A Project Proposal for.
Lecture #3 Page 1 ECE 4110– Sequential Logic Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.No Class Monday, Labor Day Holiday 2.HW#2 assigned.
Spring Introduction  Today’s tutorial focuses on introducing you to Xilinx ISE and Modelsim.  These tools are used for Verilog Coding Simulation.
ECE 477 Design Review Team 2  Fall Outline Project overviewProject overview Project-specific success criteriaProject-specific success criteria.
VHDL Project Specification Naser Mohammadzadeh. Schedule  due date: Tir 18 th 2.
Array Synthesis in SystemC Hardware Compilation Authors: J. Ditmar and S. McKeever Oxford University Computing Laboratory, UK Conference: Field Programmable.
Chapter 5: Electronic Music and Synthesizers Who uses electronic musical synthesizers? Each advance in electronic technology is followed by a concomitant.
Lecture #3 Page 1 ECE 4110–5110 Digital System Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.HW#2 assigned Due.
displayCtrlr Specification
CascadedBCDCntr&Display Aim : Capture, simulate and implement a 2-digit, loadable BCD up/down counter, with chip enable I/P (CE) and chip enable O/P (CEO).
In and Out are opposites. This is something to keep in mind when considering Input and Output. INPUT OUTPUT Ask: Does this device send information in?
 The TenCup Entertainment Table is an interactive table that enhances the game-play experience of Beirut for both the player and the spectator.
Yu Du, Yu Long Electrical & Computer Engineering
Microelectronic Systems--University of Tennessee 1 1 ECE 551–Semester Project Presentation Design of Electronic Piano Based on Spattan-3 Starter.
Floyd, Digital Fundamentals, 10 th ed Digital Fundamentals Tenth Edition Floyd © 2008 Pearson Education Chapter 1.
Microcomputer Systems Final Project “Speaker and Sound Modulation”
Part A Final Dor Obstbaum Kami Elbaz Advisor: Moshe Porian August 2012 FPGA S ETTING U SING F LASH.
November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing.
 Seattle Pacific University EE Logic System DesignAlteraBoard-2 Altera Cyclone II (484 Pin BGA) 22 Pins.
Microelectronic Systems--University of Tennessee 1 1 Mancala Ben McCue Nithiya Gajanetharan Nora D. Bull ECE 551.
Digital System Design using VHDL
Lecture 5B Block Diagrams HASH Example.
Teaching Digital Logic courses with Altera Technology
Sub- Nyquist Sampling System Hardware Implementation System Architecture Group – Shai & Yaron Data Transfer, System Integration and Debug Environment Part.
ECE 3450 M. A. Jupina, VU, 2016 Capacitance Sensor Project Goal: Creation of a digital capacitance sensor circuit where a variation in capacitance changes.
Internal Logic Analyzer Characterization presentation By: Moran Katz and Zvika Pery Mentor: Moshe Porian Dual-semester project Spring 2012.
Performed by: Or Rozenboim Gilad Shterenshis Instructor: Ina Rivkin המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון.
Internal Logic Analyzer Middle presentation-part A By: Moran Katz and Zvika Pery Mentor: Moshe Porian Dual-semester project Spring 2012.
EET 1131 Unit 4 Programmable Logic Devices
16-bit barrel shifter A Mini Project Report
Scrolling LCD using Arduino.
Backprojection Project Update January 2002
Troy Davis and Caitlin Smart
Final Project Report 64 points FFT
RTL Design Methodology Transition from Pseudocode & Interface
Voice Manipulator Department of Electrical & Computer Engineering
ECE Computer Engineering Design Project
Fairmont Park Baptist Church Technical Support Ministry
Laser Harp Team: Peter Crinklaw Qiushi Jiang Edwin Rodriguez.
FPGA Implementation of Multicore AES 128/192/256
ECE 434 Advanced Digital System L13
ECE Computer Engineering Design Project
RTL Design Methodology
RTL Design Methodology Transition from Pseudocode & Interface
♪ Embedded System Design: Synthesizing Music Using Programmable Logic
Presentation transcript:

Microelectronic Systems--University of Tennessee 1 1 Music Synthesizer Design Christopher Boyd Ki Shin Electrical & Computer Engineering University of Tennessee Knoxville, TN

Microelectronic Systems--University of Tennessee 2 2 OUTLINE Design Requirements –Board Design Overview –Module Hierarchy –Note Signal »Pitch –Synthesizer Pre-Synthesis Simulation Post-Synthesis Simulation Conclusion

Microelectronic Systems--University of Tennessee 3 3 Design Requirements RequirementsRealized Functions Play Music from Stored Music File, with the ability to switch between the four octaves. (1)Memory Controller for Read/Write (Proposal)  Used VHDL Sub Module for Sheet Music (Final) (2) Music Synthesizer  Able to make stereo sounds from Sheet Music (3) Synthesize four different octaves  Able to achieve 4 octave harmony (4) Button control for changing octave (Proposal)  Used Switches to make Synchronization (Final)

Microelectronic Systems--University of Tennessee 4 4 Spartan-3A Board We decided to use the Spartan-3A, since it had a 3.5 mm jack for music output.

Microelectronic Systems--University of Tennessee 5 5 Spartan-3A (Xilinx ISE)

Microelectronic Systems--University of Tennessee 6 6 Spartan-3A (FPGA Editor)

Microelectronic Systems--University of Tennessee 7 7 X200 Synthesis (ISE)

Microelectronic Systems--University of Tennessee 8 8 Altera Cyclone II (Quartus)

Microelectronic Systems--University of Tennessee 9 9 Mentor Graphics Block Diagram

Microelectronic Systems--University of Tennessee 10 Design Overview with I/O Block Block Diagram Synthesizer Specify File (Controller) Specify File (Controller) Speaker (Left) Change Scale Switch (0~3) Sheet Music (Sub Module) Sheet Music (Sub Module) Christopher Boyd Ki Shin Speaker (Right)

Microelectronic Systems--University of Tennessee 11 Hierarchy of Modules Music.vhd (Main Controller + Music Synthesizer) Music.vhd (Main Controller + Music Synthesizer) Music 3 : Jingle Bell (Melody Tone) Music 3 : Jingle Bell (Melody Tone) Music 2 : Amazing Grace (Melody Tone) Music 2 : Amazing Grace (Melody Tone) Music 1 : Rocky Top Music 1 : Rocky Top Music 3_1 : Jingle Bell (Base Tone) Music 3_1 : Jingle Bell (Base Tone) Music 2_1 : Amazing Grace (Base Tone) Music 2_1 : Amazing Grace (Base Tone)

Microelectronic Systems--University of Tennessee 12 Explanation of Note Signal Signal (Note) – 8 bits 4 bits  16 states : Assign Note Scale (C, C#, D, …. ) 1 bit  2 states : Assign High Tone 3 bit  8 states : Assign Duration (Whole / Half … ) If Note = “ ”, that means EOF (End of File)

Microelectronic Systems--University of Tennessee 13 Pitch of Notes

Microelectronic Systems--University of Tennessee 14 Synthesizer 50 MHz Clock Clock Divider Music file Note Signal Switch Input Octave Toggle 1/0 Left Speaker Left Speaker Right Speaker Right Speaker

Microelectronic Systems--University of Tennessee 15 Pre – Synthesis Simulation By Swt input, music is changed Out By Octave input, frequency is changed Out Freq. Out Freq.

Microelectronic Systems--University of Tennessee 16 Post – Synthesis Simulation By Swt input, music is changed By Octave input, frequency is changed

Microelectronic Systems--University of Tennessee 17 Issues Encountered Since the signal sent to the speakers is digital (0 or 1) rather than analog, we couldn’t output more than one tone (per speaker) at once. Attempting to half the volume didn’t work either. (by sending 1010 instead of 1111) –Being able to vary the volume would have been useful for reverb as well as multiple tones.

Microelectronic Systems--University of Tennessee 18 CONCLUSIONS We were limited by the hardware we had on hand. –Can play, at most, two tones at once with stereo sound. Parallel Processing –We could play different music at the same time and select the file by using switches. –For parallel processing, synchronization is very important. Synchronization issues –When changing songs, the two parts could desync. –We fixed this by resetting the note being played, when we change songs.

Microelectronic Systems--University of Tennessee 19 Appendix – Rocky Top