Scalable Many-Core Memory Systems Lecture 3, Topic 2: Emerging Technologies and Hybrid Memories Prof. Onur Mutlu HiPEAC ACACES Summer School 2013 July 17, 2013

What Will You Learn in This Course? Scalable Many-Core Memory Systems  July 15-19, 2013 Topic 1: Main memory basics, DRAM scaling Topic 2: Emerging memory technologies and hybrid memories Topic 3: Main memory interference and QoS Topic 4 (unlikely): Cache management Topic 5 (unlikely): Interconnects Major Overview Reading:  Mutlu, “Memory Scaling: A Systems Architecture Perspective,” IMW

Readings and Videos

Course Information Website for Course Slides and Papers    Lecture notes and readings are uploaded My Contact Information  Onur Mutlu    (my cell phone)  Find me during breaks and/or any time. 4

Memory Lecture Videos Memory Hierarchy (and Introduction to Caches)  9REog9jDnPDTG6IJ&index=22 9REog9jDnPDTG6IJ&index=22 Main Memory  d59REog9jDnPDTG6IJ&index=25 d59REog9jDnPDTG6IJ&index=25 Memory Controllers, Memory Scheduling, Memory QoS  d59REog9jDnPDTG6IJ&index=26 d59REog9jDnPDTG6IJ&index=26  d59REog9jDnPDTG6IJ&index=27 d59REog9jDnPDTG6IJ&index=27 Emerging Memory Technologies  d59REog9jDnPDTG6IJ&index=35 d59REog9jDnPDTG6IJ&index=35 Multiprocessor Correctness and Cache Coherence  VZKMgItDM&list=PL5PHm2jkkXmidJOd59REog9jDnPDTG6IJ&index=32 VZKMgItDM&list=PL5PHm2jkkXmidJOd59REog9jDnPDTG6IJ&index=32 5

Readings for Topic 1 (DRAM Scaling) Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA Kim et al., “A Case for Exploiting Subarray-Level Parallelism in DRAM,” ISCA Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA Seshadri et al., “RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data,” CMU CS Tech Report David et al., “Memory Power Management via Dynamic Voltage/Frequency Scaling,” ICAC Ipek et al., “Self Optimizing Memory Controllers: A Reinforcement Learning Approach,” ISCA

Readings for Topic 2 (Emerging Technologies) Lee, Ipek, Mutlu, Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” ISCA 2009, CACM 2010, Top Picks Qureshi et al., “Scalable high performance main memory system using phase-change memory technology,” ISCA Meza et al., “Enabling Efficient and Scalable Hybrid Memories,” IEEE Comp. Arch. Letters Yoon et al., “Row Buffer Locality Aware Caching Policies for Hybrid Memories,” ICCD 2012 Best Paper Award. Meza et al., “A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory,” WEED Kultursay et al., “Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative,” ISPASS

Readings for Topic 3 (Memory QoS) Moscibroda and Mutlu, “Memory Performance Attacks,” USENIX Security Mutlu and Moscibroda, “Stall-Time Fair Memory Access Scheduling,” MICRO Mutlu and Moscibroda, “Parallelism-Aware Batch Scheduling,” ISCA 2008, IEEE Micro Kim et al., “ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers,” HPCA Kim et al., “Thread Cluster Memory Scheduling,” MICRO 2010, IEEE Micro Muralidhara et al., “Memory Channel Partitioning,” MICRO Ausavarungnirun et al., “Staged Memory Scheduling,” ISCA Subramanian et al., “MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,” HPCA Das et al., “Application-to-Core Mapping Policies to Reduce Memory System Interference in Multi-Core Systems,” HPCA

Readings for Topic 3 (Memory QoS) Ebrahimi et al., “Fairness via Source Throttling,” ASPLOS 2010, ACM TOCS Lee et al., “Prefetch-Aware DRAM Controllers,” MICRO 2008, IEEE TC Ebrahimi et al., “Parallel Application Memory Scheduling,” MICRO Ebrahimi et al., “Prefetch-Aware Shared Resource Management for Multi-Core Systems,” ISCA

Readings in Flash Memory Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrian Cristal, Osman Unsal, and Ken Mai, "Error Analysis and Retention-Aware Error Management for NAND Flash Memory" Intel Technology Journal (ITJ) Special Issue on Memory Resiliency, Vol. 17, No. 1, May "Error Analysis and Retention-Aware Error Management for NAND Flash Memory" Intel Technology Journal Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai, "Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling" Proceedings of the Design, Automation, and Test in Europe Conference (DATE), Grenoble, France, March Slides (ppt) "Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling"Design, Automation, and Test in Europe ConferenceSlides (ppt) Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrian Cristal, Osman Unsal, and Ken Mai, "Flash Correct-and-Refresh: Retention-Aware Error Management for Increased Flash Memory Lifetime" Proceedings of the 30th IEEE International Conference on Computer Design (ICCD), Montreal, Quebec, Canada, September Slides (ppt) (pdf) "Flash Correct-and-Refresh: Retention-Aware Error Management for Increased Flash Memory Lifetime"30th IEEE International Conference on Computer DesignSlides (ppt)(pdf) Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai, "Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis" Proceedings of the Design, Automation, and Test in Europe Conference (DATE), Dresden, Germany, March Slides (ppt) "Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis"Design, Automation, and Test in Europe ConferenceSlides (ppt) 10

Online Lectures and More Information Online Computer Architecture Lectures  Eog9jDnPDTG6IJ Eog9jDnPDTG6IJ Online Computer Architecture Courses  Intro:  Advanced:  Advanced: Recent Research Papers   n n 11

Emerging Memory Technologies

Agenda Major Trends Affecting Main Memory Requirements from an Ideal Main Memory System Opportunity: Emerging Memory Technologies Conclusions Discussion 13

Major Trends Affecting Main Memory (I) Need for main memory capacity and bandwidth increasing Main memory energy/power is a key system design concern DRAM technology scaling is ending 14

Trends: Problems with DRAM as Main Memory Need for main memory capacity and bandwidth increasing  DRAM capacity hard to scale Main memory energy/power is a key system design concern  DRAM consumes high power due to leakage and refresh DRAM technology scaling is ending  DRAM capacity, cost, and energy/power hard to scale 15

Agenda Major Trends Affecting Main Memory Requirements from an Ideal Main Memory System Opportunity: Emerging Memory Technologies Conclusions Discussion 16

Traditional  Enough capacity  Low cost  High system performance (high bandwidth, low latency) New  Technology scalability: lower cost, higher capacity, lower energy  Energy (and power) efficiency  QoS support and configurability (for consolidation) 17 Requirements from an Ideal Memory System

Traditional  Higher capacity  Continuous low cost  High system performance (higher bandwidth, low latency) New  Technology scalability: lower cost, higher capacity, lower energy  Energy (and power) efficiency  QoS support and configurability (for consolidation) 18 Requirements from an Ideal Memory System Emerging, resistive memory technologies (NVM) can help

Review: Solutions to the DRAM Scaling Problem Two potential solutions  Tolerate DRAM (by taking a fresh look at it)  Enable emerging memory technologies to eliminate/minimize DRAM Do both  Hybrid memory systems 19

Solution 1: Tolerate DRAM Overcome DRAM shortcomings with  System-DRAM co-design  Novel DRAM architectures, interface, functions  Better waste management (efficient utilization) Key issues to tackle  Reduce refresh energy  Improve bandwidth and latency  Reduce waste  Enable reliability at low cost Liu, Jaiyen, Veras, Mutlu, “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA Kim, Seshadri, Lee+, “A Case for Exploiting Subarray-Level Parallelism in DRAM,” ISCA Lee+, “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA Liu+, “An Experimental Study of Data Retention Behavior in Modern DRAM Devices” ISCA’13. Seshadri+, “RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data,”

Solution 2: Emerging Memory Technologies Some emerging resistive memory technologies seem more scalable than DRAM (and they are non-volatile) Example: Phase Change Memory  Expected to scale to 9nm (2022 [ITRS])  Expected to be denser than DRAM: can store multiple bits/cell But, emerging technologies have shortcomings as well  Can they be enabled to replace/augment/surpass DRAM? Lee, Ipek, Mutlu, Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” ISCA 2009, CACM 2010, Top Picks Meza, Chang, Yoon, Mutlu, Ranganathan, “Enabling Efficient and Scalable Hybrid Memories,” IEEE Comp. Arch. Letters Yoon, Meza et al., “Row Buffer Locality Aware Caching Policies for Hybrid Memories,” ICCD 2012 Best Paper Award. 21

Hybrid Memory Systems Meza+, “Enabling Efficient and Scalable Hybrid Memories,” IEEE Comp. Arch. Letters, Yoon, Meza et al., “Row Buffer Locality Aware Caching Policies for Hybrid Memories,” ICCD 2012 Best Paper Award. CPU DRA MCtrl Fast, durable Small, leaky, volatile, high-cost Fast, durable Small, leaky, volatile, high-cost Large, non-volatile, low-cost Slow, wears out, high active energy Large, non-volatile, low-cost Slow, wears out, high active energy PCM Ctrl DRAM Phase Change Memory (or Tech. X) Hardware/software manage data allocation and movement to achieve the best of multiple technologies

Agenda Major Trends Affecting Main Memory Requirements from an Ideal Main Memory System Opportunity: Emerging Memory Technologies Conclusions Discussion 23

The Promise of Emerging Technologies Likely need to replace/augment DRAM with a technology that is  Technology scalable  And at least similarly efficient, high performance, and fault-tolerant or can be architected to be so Some emerging resistive memory technologies appear promising  Phase Change Memory (PCM)?  Spin Torque Transfer Magnetic Memory (STT-MRAM)?  Memristors?  And, maybe there are other ones  Can they be enabled to replace/augment/surpass DRAM? 24

Agenda Major Trends Affecting Main Memory Requirements from an Ideal Main Memory System Opportunity: Emerging Memory Technologies  Background  PCM (or Technology X) as DRAM Replacement  Hybrid Memory Systems Conclusions Discussion 25

Charge vs. Resistive Memories Charge Memory (e.g., DRAM, Flash)  Write data by capturing charge Q  Read data by detecting voltage V Resistive Memory (e.g., PCM, STT-MRAM, memristors)  Write data by pulsing current dQ/dt  Read data by detecting resistance R 26

Limits of Charge Memory Difficult charge placement and control  Flash: floating gate charge  DRAM: capacitor charge, transistor leakage Reliable sensing becomes difficult as charge storage unit size reduces 27

Emerging Resistive Memory Technologies PCM  Inject current to change material phase  Resistance determined by phase STT-MRAM  Inject current to change magnet polarity  Resistance determined by polarity Memristors  Inject current to change atomic structure  Resistance determined by atom distance 28

What is Phase Change Memory? Phase change material (chalcogenide glass) exists in two states:  Amorphous: Low optical reflexivity and high electrical resistivity  Crystalline: High optical reflexivity and low electrical resistivity 29 PCM is resistive memory: High resistance (0), Low resistance (1) PCM cell can be switched between states reliably and quickly

How Does PCM Work? Write: change phase via current injection  SET: sustained current to heat cell above Tcryst  RESET: cell heated above Tmelt and quenched Read: detect phase via material resistance  amorphous/crystalline 30 Large Current SET (cryst) Low resistance  Small Current RESET (amorph) High resistance Access Device Memory Element  Photo Courtesy: Bipin Rajendran, IBMSlide Courtesy: Moinuddin Qureshi, IBM

Opportunity: PCM Advantages Scales better than DRAM, Flash  Requires current pulses, which scale linearly with feature size  Expected to scale to 9nm (2022 [ITRS])  Prototyped at 20nm (Raoux+, IBM JRD 2008) Can be denser than DRAM  Can store multiple bits per cell due to large resistance range  Prototypes with 2 bits/cell in ISSCC’08, 4 bits/cell by 2012 Non-volatile  Retain data for >10 years at 85C No refresh needed, low idle power 31

Phase Change Memory Properties Surveyed prototypes from (ITRS, IEDM, VLSI, ISSCC) Derived PCM parameters for F=90nm Lee, Ipek, Mutlu, Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” ISCA

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Phase Change Memory Properties: Latency Latency comparable to, but slower than DRAM Read Latency  50ns: 4x DRAM, x NAND Flash Write Latency  150ns: 12x DRAM Write Bandwidth  5-10 MB/s: 0.1x DRAM, 1x NAND Flash 34

Phase Change Memory Properties Dynamic Energy  40 uA Rd, 150 uA Wr  2-43x DRAM, 1x NAND Flash Endurance  Writes induce phase change at 650C  Contacts degrade from thermal expansion/contraction  10 8 writes per cell  x DRAM, 10 3 x NAND Flash Cell Size  9-12F 2 using BJT, single-level cells  1.5x DRAM, 2-3x NAND (will scale with feature size, MLC) 35

Phase Change Memory: Pros and Cons Pros over DRAM  Better technology scaling  Non volatility  Low idle power (no refresh) Cons  Higher latencies: ~4-15x DRAM (especially write)  Higher active energy: ~2-50x DRAM (especially write)  Lower endurance (a cell dies after ~10 8 writes) Challenges in enabling PCM as DRAM replacement/helper:  Mitigate PCM shortcomings  Find the right way to place PCM in the system  Ensure secure and fault-tolerant PCM operation 36

PCM-based Main Memory: Research Challenges Where to place PCM in the memory hierarchy?  Hybrid OS controlled PCM-DRAM  Hybrid OS controlled PCM and hardware-controlled DRAM  Pure PCM main memory How to mitigate shortcomings of PCM? How to minimize amount of DRAM in the system? How to take advantage of (byte-addressable and fast) non- volatile main memory? Can we design specific-NVM-technology-agnostic techniques? 37

PCM-based Main Memory (I) How should PCM-based (main) memory be organized? Hybrid PCM+DRAM [Qureshi+ ISCA’09, Dhiman+ DAC’09, Meza+ IEEE CAL’12] :  How to partition/migrate data between PCM and DRAM 38

Hybrid Memory Systems: Challenges Partitioning  Should DRAM be a cache or main memory, or configurable?  What fraction? How many controllers? Data allocation/movement (energy, performance, lifetime)  Who manages allocation/movement?  What are good control algorithms?  How do we prevent degradation of service due to wearout? Design of cache hierarchy, memory controllers, OS  Mitigate PCM shortcomings, exploit PCM advantages Design of PCM/DRAM chips and modules  Rethink the design of PCM/DRAM with new requirements 39

PCM-based Main Memory (II) How should PCM-based (main) memory be organized? Pure PCM main memory [Lee et al., ISCA’09, Top Picks’10] :  How to redesign entire hierarchy (and cores) to overcome PCM shortcomings 40

Aside: STT-RAM Basics Magnetic Tunnel Junction (MTJ)  Reference layer: Fixed  Free layer: Parallel or anti-parallel Cell  Access transistor, bit/sense lines Read and Write  Read: Apply a small voltage across bitline and senseline; read the current.  Write: Push large current through MTJ. Direction of current determines new orientation of the free layer. Kultursay et al., “Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative,” ISPASS 2013 Reference Layer Free Layer Barrier Reference Layer Free Layer Barrier Logical 0 Logical 1 Word Line Bit Line Access Transistor MTJ Sense Line

Aside: STT MRAM: Pros and Cons Pros over DRAM  Better technology scaling  Non volatility  Low idle power (no refresh) Cons  Higher write latency  Higher write energy  Reliability? Another level of freedom  Can trade off non-volatility for lower write latency/energy (by reducing the size of the MTJ) 42

Agenda Major Trends Affecting Main Memory Requirements from an Ideal Main Memory System Opportunity: Emerging Memory Technologies  Background  PCM (or Technology X) as DRAM Replacement  Hybrid Memory Systems Conclusions Discussion 43

An Initial Study: Replace DRAM with PCM Lee, Ipek, Mutlu, Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” ISCA  Surveyed prototypes from (e.g. IEDM, VLSI, ISSCC)  Derived “average” PCM parameters for F=90nm 44

Results: Naïve Replacement of DRAM with PCM Replace DRAM with PCM in a 4-core, 4MB L2 system PCM organized the same as DRAM: row buffers, banks, peripherals 1.6x delay, 2.2x energy, 500-hour average lifetime Lee, Ipek, Mutlu, Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” ISCA

Architecting PCM to Mitigate Shortcomings Idea 1: Use multiple narrow row buffers in each PCM chip  Reduces array reads/writes  better endurance, latency, energy Idea 2: Write into array at cache block or word granularity  Reduces unnecessary wear 46 DRAM PCM

Results: Architected PCM as Main Memory 1.2x delay, 1.0x energy, 5.6-year average lifetime Scaling improves energy, endurance, density Caveat 1: Worst-case lifetime is much shorter (no guarantees) Caveat 2: Intensive applications see large performance and energy hits Caveat 3: Optimistic PCM parameters? 47

Agenda Major Trends Affecting Main Memory Requirements from an Ideal Main Memory System Opportunity: Emerging Memory Technologies  Background  PCM (or Technology X) as DRAM Replacement  Hybrid Memory Systems Conclusions Discussion 48

Hybrid Memory Systems Meza, Chang, Yoon, Mutlu, Ranganathan, “Enabling Efficient and Scalable Hybrid Memories,” IEEE Comp. Arch. Letters, CPU DRA MCtrl Fast, durable Small, leaky, volatile, high-cost Fast, durable Small, leaky, volatile, high-cost Large, non-volatile, low-cost Slow, wears out, high active energy Large, non-volatile, low-cost Slow, wears out, high active energy PCM Ctrl DRAM Phase Change Memory (or Tech. X) Hardware/software manage data allocation and movement to achieve the best of multiple technologies

One Option: DRAM as a Cache for PCM PCM is main memory; DRAM caches memory rows/blocks  Benefits: Reduced latency on DRAM cache hit; write filtering Memory controller hardware manages the DRAM cache  Benefit: Eliminates system software overhead Three issues:  What data should be placed in DRAM versus kept in PCM?  What is the granularity of data movement?  How to design a low-cost hardware-managed DRAM cache? Two idea directions:  Locality-aware data placement [Yoon+, ICCD 2012]  Cheap tag stores and dynamic granularity [Meza+, IEEE CAL 2012] 50