N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM Test Insert and Scribe-line Metal 2 Passivation Planarisation AlSiCu BPSG Spacer FOX FOX FOX FOX LDD Arsenic Implant BF2 S/D Implant As+ S/D Implant N-Well P-Well N-Well Capacitor PMOS NMOS P+ Substrate

Overview Integrated Circuit Manufacturing Process Mask Design and Layout Main Fabrication Process Transistor Fabrication Step by Step Electrical Characterization and Testing Fabrication Documents (Runcard) Preparation

The making of transistor Circuit design Mask/layout design Mask making and artwork Fabrication process Device testing – for parametric and functional test Packaging and Reliability Test

Step 1: Logic Design

Step 2: Circuit Design

Step 3: Layout Design

Mask Making and Artwork

Fabrication Process

Step 11: Wafer Probe, Scribe & dice

Step 12: Die Attach, Wire Bonding, & Encapsulation

Step 13: Final Test

Mask Design

MOSFET Masking Step Mask 1: Source Drain Mask Mask 2: Gate Mask Mask 3: Contact mask Mask 4: Metallization Mask

Introduction Mask design is very important before fabrication process can be done. Design rules must be followed to prevent defect in the process. In this design, gate length is varied from 30um, 50um, 100um, 150um, 200um and 300um. Different gate length will have different gate mask and different distance from source to drain. The smaller the gate size, the better the transistor in speed.

Circuit, layout and cross section of NMOS transistor In NMOS design, NMOS circuit is transferred to layout design. Then, mask can be design to fabricate NMOS transistor.

MASK 1: Source Drain Mask Mask 1 is used to control the heavily phosphorus doped and create the source and drain region of the n_channel device. Layout 1: Source and Drain

Mask 2: Gate Mask Mask 2 is used to remove the thick oxide layer and grow a very high quality of thin oxide. Layout 2: Layout 1 and gate

Mask 3: Contact mask Mask 3 is used to pattern the contact holes. Etching will open the holes. Layout 3: Layout 2 and contact

Mask 4: Metallization Mask Mask 4 is used to pattern the connection. The uncovered Aluminum film will be removed during etching process. Layout 4: Layout 3 and metallization

Mask Design (Step by Step)

Photo Mask Preparation Apply AutoCAD to design the masks Transfer the pattern to high resolution printer

Mask Design Step Step 1: Set frame and wafer size dimension Step 2: Design alignment mark Step 3: Design source and drain mask (Mask 1) block and duplicate to the whole wafer. Step 4: Design gate mask (Mask 2) block and duplicate to the whole wafer. Then, inverse the alignment mark to change the polarity.

Step 5:. Design contact mask (Mask 3) block Step 5: Design contact mask (Mask 3) block and duplicate to the whole wafer. Step 6: Design Metallization mask (Mask 4) block and duplicate to the whole mask. Step 7: Print on transparency film using high resolution printer.

Step 1: Set frame and wafer size dimension The frame size is set to 20” x 12” (A4 paper size). The wafer diameter is set to 4” and the wafer block is set to 6” x 6”. Then the design unit is set to millimeter or micron depend on the designer’s convenience.

Step 2: Alignment Mark design Alignment mark is used to align wafer between layer to layer during the fabrication process. First, design the alignment block. Then, design the cross an insert it inside the block.

Step 3: Design source and drain mask First, design the mask block. Then, design the source and drain region which is uncovered and designed with desired dimension. At this mask, the polarity of the alignment block is reversed. The cross is open and the block is opaque.

Step 4: Design gate mask The red block is the gate mask, it is drawn before the white area. The white area on the red layer is the gate region. Maintain the mask design

Step 5: Design contact mask The brown block is the gate mask. The white rectangle is the contact region. Maintain the mask design

Step 6: Design metallization mask The Metallization mask is used for routing purposes. The unprotected region will be etched away whereby the exposed Aluminum area will be removed. Maintain the mask design

Actual Transparency Masks

Q & A

EQUIPMENTS AND CONSUMABLES

Equipments FABRICATION EQUIPMENTS PURPOSES Dry/Wet Oxidation Furnace For wet and dry oxidation process N/P Dope Diffusion Furnace For n&p -type diffusion process Plasma Enhanced chemical Vapor Thin film Deposition (PECVD) Deposition Mask Aligner and Exposure System For mask and wafer alignment and exposure Aluminium Evaporator Aluminium deposition Hot Plate For dehydrate wafer Electrical Probe Station To conduct electrical test on wafer level Micrometer For measuring wafer thickness Photoresist Spinner Photoresist deposition by spin-on Step Height Measurement System To measure the step height of metal surface Low Power Optical Microscope To observe wafer during process

Equipments FABRICATION EQUIPMENTS PURPOSES Conduction Gauge To determine wafer carrier type CV Test Station To conduct capacitance and voltage test Four Point Probe For measuring sheet resistance IV Test Station To measure the current and voltage characteristics Diamond Scriber Marking lot number on wafer Spectrophotometer To measure thin film thickness Wet etch bench To perform wet chemical etching Buffered Etch Oxide (BOE) Tank Aluminium Etchant Tank Developer Tank Spin Rinse Dryer Wet process bench To perform wet cleaning process Wet Bench Tank

Consumables CONSUMABLES PURPOSES Hydrofluoric Acid Solution To remove native oxide on silicon wafer Deionized Water For rinsing and cleaning wafers Positive/Negative Photoresist Positive/Negative masking coating layer Photoresist Developer To remove resist after exposure Buffered Etch Oxide For etching exposed and unwanted oxide Aluminium Etchant For etching aluminium 100 mm, p-type, boron-doped As the starting material <100> silicon wafer Liquid/solid Phosphorus n-type diffusion source Liquid/solid Boron p-type diffusion source Transparencies As wafer mask

MICRO FABRICATION CLEANROOM

Teaching fab Completed in December 2003 The size of the cleanroom built is approximately 115m2 Cleanliness class from ISO Class 5 to ISO Class 8.

YELLOW ROOM (ISO CLASS 5)

WHITE ROOM (ISO CLASS 6)

CHARACTERIZATION ROOM (ISO CLASS 6)

Oxidation Furnace ( WET / DRY)

Diffusion Furnace ( n-type / p- type)

Physical Vapor Deposition system

Photolithography Module

Wet Etching Module

Wet Cleaning Module

Wafer Test Module

Wafer Characterization Module

Scanning Electron Microscope Module

E-beam Lithography Module

Cleanroom Facilities Gas Corridor Scrubber System DI Water System Electrical Main Switch Board

Main Fabrication Process

Fabrication Process

Pre-Oxidation Clean Cycle The SC-1 (RCA) clean is used to remove particles and organic materials by oxidizing the particle NH4OH : H2O2 : H2O with the ratio 1 : 4 : 50 Temperature ~75℃ with 10 minutes duration and rinse by DI water ~3 minutes

SC-1 Clean Cycle System SC-1 Clean Cycle System DI Water System

Diffusion Junction Depth – Spreading Resistance Measurement

Diffusion (cont.) The relation among temperature, duration and Junction Depth 60 minutes N2:O2 = 4:1 1200 ℃ N2:O2 = 4:1

Diffusion (cont.) Different structures have different junction depth in the same condition 1100 ℃ 60minutes N2:O2 = 1:1

Diffusion (cont.) Sheet Resistance

Diffusion impurities The material employed in a diffusion process is termed the diffusion source. Many types of materials can be applied as diffusion sources because the diffusion processes for the Si-base device have many distinct requirements. The impurities can be classified into two types for semiconductor manufacturing: "acceptor" and "donor". Acceptors can be adopted to form a "p-type" semiconductor, and donors can be applied to create an "n-type" semiconductor. NMOS PMOS http://www.ndl.org.tw/english/icfab/Process/07-Diffusion/m3-7-2.htm

Photolithography Flow 1.PR Coating 5.Exposure 2.Wafer Spin 6.Develop 3.Soft Bake Photolithography Flow 7.Inspection 4.Mask Align 8.Etching

Photolithographic Alignment – Contrast of Alignment Mark Exposure Bias – Inaccurate Critical Dimension on Photo Masks

Transistor Fabrication (Step by Step Process)

n-channel MOSFET Fabrication The device fabrication steps are shown for n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (FET).  All photolithography processes are shown by means of animation.  The steps shown here are the most detailed and serve as basis for the next few applets showing the device fabrication. A lightly doped p-type Si wafer

Oxide Grown For NMOS process, the starting material is a P-type lightly doped, <100>-oriented, polished silicon wafer. The first step is to form the SiO2 layer(0.5 - 1um thick) by thermal oxidation. The oxidation temperature is generally in the range of 900 - 1200 degree C, and the typical gas flow rate is about 1cm/s.

Photoresist Applied Following oxidation, several drops of positive Photoresist(e.g. Shipley S1818) are dropped on the wafer. The wafer is spun at about 3000rpm to be uniformly spread out.After the spinning step, the wafer is given a pre-exposure baking (80 - 100 degree C) to remove the solvent from the PR film and improve adhesion to the substrate.

PR Developed Third step is to define the active area (Drain and Source regions) by photolithography.The PR layer not covered by the mask undergoes a chemical change by UV light and is removed by the spraying the wafer with the developing solution(e.g. Shipley MF319). The final remaining PR is a copy of the pattern on the mask. Finally,the wafer is rinsed and spin-dried, and then baked again so that the PR can resist the strong acid used to etch the exposed oxide layer.

Oxdie Etched For SiO2 etching, HydroFluoric(HF) acid is usually used because it attacks oxide, but not silicon or PR. Therefore, the HydroFluoric(HF) acid etches away the oxide in the openings in the PR, and stops at the silicon surface.

PR Removed After SiO2 etching, PR is stripped by using either a solvent (Aceton) or a plasma oxidation, leaving behind an insulator pattern that is the same as the opaque image on the mask.

Phosphorus Diffused After stripping the PR,a two-step diffusion process is used to form drain and source regions, in which Phosphorus predeposition is first formed under a Constant-Surface-Concentration Condition(CSCC) and then is followed by a drive-in diffusion under a Constant-Total-Dopant Condition(CTDC). Finally, a thin layer of Phosphosilicate Glass on the wafer is removed by HF

Field Oxide Grown After the forming the drain and source regions, additional oxide layer is grown from thermal oxidation as before. The Phosphorus spreads out by diffusion during this furnace operation, but the concentration are still much higher than that of the substrate doping.

PR Applied The second photolithography process is done to remove the oxide, defining a gate region. The same procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

PR Developed The second photolithography process is done to remove the oxide, defining a gate region. The same procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

Oxide Etched The second photolithography process is done to remove the oxide, defining a gate region. The same procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

PR Stripped The second photolithography process is done to remove the oxide, defining a gate region. The same procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

Gate Oxide Grown After the second photolithography, a very thin gate oxide layer(a few hundred angstroms) is grown by thermal oxidation.

PR Applied The third photolithography process is done to remove the oxide, defining contact holes. The same procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

PR Developed The third photolithography process is done to remove the oxide, defining contact holes. The same procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

Oxide Etched The third photolithography process is done to remove the oxide, defining contact holes. The same procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

PR Removed The third photolithography process is done to remove the oxide, defining contact holes. The same procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing -> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

Aluminium Film Deposited A metal such as Aluminum is then evaporated on the whole substrate surface(a few thousand angstrom thick) under high-vacuum condition.This method is attractive because it is simple and inexpensive and produces no ionizing radiation.The Al layer will form electrical contacts later.

PR Applied The final lithography process is done to remove the Al-layer, defining a contact pattern. The same procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

PR Developed The final lithography process is done to remove the Al-layer, defining a contact pattern. The same procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

Aluminium Interconnect Etched The final lithography process is done to remove the Al-layer, defining a contact pattern. The same procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

Completion of NMOS Fabrication After the final PR stripping, all the NMOS fabrication steps are completed.

Expected Product – Fabricated MOSFET

Electrical Characterization and Testing

The Profile of MOS Transistor The curves of drain current versus drain voltage The profile of the finished wafer

The Characteristics of PMOS Threshold voltage of the PMOS is about –3V The resistance of the resistor is about 5 kΩ

The Characteristics of PMOS (cont.)

MOSFET IV Characteristics PMOS NMOS

Fabrication Documents (Runcard) Preparation

Process Flow Development Diagram

Runcard Checklist Process runcard Measurement sheet Rework sheet Equipments list Consumables list Design specification Complete Mask Design

Process Runcard No. of process steps = 71 No of process module = 11 Shall include the following information; Step number Equipment ID Wafer out Time in/out Date out Remarks

Measurement sheet Total Number of measurement = 35 Sheet Resistance Measurement = 6 Oxide Thickness Measurement = 9 Resist Thickness Measurement = 4 CD Measurement = 7

Rework sheet Only for lithography process

Actual Transparency Masks

Thanks