USB 3.0 Write Blocker Team Dec 1108 Design review presentation Team member Client Info Advisor Chen Zhao Electronic Crime Institution at Des Moines Area Community College Dr. Zhao Zhang Elphas Sang Joe Lane jrlane@dmacc.edu Yan Fang

Project Plan and High Level Description

Problem Statement USB 3.0 to SATA data adapter Correct design of a command filter that drops writing commands

Conceptual Sketch Use case scenario

Conceptual Sketch (cont’d.) Massive Storage Device on USB is complex in firmware organization. They support both USB protocols required for universal USB devices and SCSI standard between computer and peripheral devices. An embedded system that function as a USB massive storage device has the following list of requirements. A smart microcontroller that manages the system operations A USB device controller, which is another microcontroller that interfaces to the USB port. This controller can also be integrated with the device’s own CPU into one microcontroller A generic harddrive (flash drive) interfacing to the device’s CPU The device effectively responds to generic USB requests on the bus The device effectively responds to SCSI commands received in USB transfers. These commands are industry standards for storage media.

Conceptual Sketch (cont’d.) About embedded hosts An embedded system working as a USB host for a hard drive or flash drive is expected to perform the following functions. Issue USB requests and initiate other events on the bus to identify attached devices and manage traffic and power on the bus Issue USB mass-storage requests that ask for status info or specify actions for the device to perform Issue SCSI commands in USB transfers. The commands read and write blocks of data in the storage media, request status info and control the device operation

Functional Requirements Data Bridge between USB 3.0 and SATA This device acts as bridge for dataflow. It processes data transfer and controls data package. Lossless Data Transfer Data transfer does not allow any information loss. The data transfer should not be affected by the blocker except that no writing operation to hard drive is allowed. Efficiency and latency issue Although efficiency depends on specific microcontroller hardware, firmware also plays a great role on the quality and usability of the product. A bad program may lag the hardware efficiency it should have

Non-Functional requirements Product Quality (Reliability) The ability of a system or component to perform its required functions under stated conditions for a specified period of time. Portability The ability for the device to be moved from point A to point B. The device may easily be used on different computers and for different hard drives. Maintainability The product is maintainable which means the hardware configuration is well documented and may be updated and improved for later on projects. Testability Tests are easily performed on the device. And these tests demonstrate the capability of the final product. Usability Ease-of-use requirements address the factors that constitute the capacity of the software to be understood, learned, and used by its intended users.

Technical consideration Choice of device microcontroller Some typical controllers with support for ATA/ATAPI: Texas Instruments TUSB6250 USB 2.0 to ATA/TAPI bridge controller Philips Semiconductor ISP 1583 Hi-Speed Universal Serial Bus peripheral controller SMSC SW6313 Single Chip USB 3.0 to SATA Bridge Software Development Kits (SDK) for firmware update need extra technical support from the microcontroller manufacturer for example, Symwave also provides a variety of host application Software Development Kits (SDK) for firmware update, Security password and Mass Production Tools

Market survey What makes our project unique? Very few similar product exists around the market for USB 3.0 There are quite a few products for USB 2.0 with similar functions around the market nowadays. For example, Taleau provides solutions for USB 2.0 to SATA bridge. ForensicPC has a series of Forensic write-block products. But there is still no USB 3.0 blocker product in the market. In 2009, Fujitsu Microelectronics shipped its first generation of USB 3.0-Serial SATA bridge IC. MB86C30A incorporates USB and SATA signal communication control circuits, protocol and command control circuits with a high-speed encryption/decryption engine on a single device.

Potential risks Schedule Risks Development Board Choice is the first step of the project and is the crucial step. A rational choice should be made considering the difficulty level of implementation and reliability of the final product. Technical Risks The hardware configuration consists of module implementation and integration. This is a complex procedure and it takes a long time to put a module into work. Operational Risks Improper operation on the device (especially during the testing process) may cause irreversible hardware damage.

Cost Estimate USB3.0 to Sata Bridge Chip About $30 Development Kit For the Chip About $100 Programming Board and Tools to be announced Other Resources About $70 Total Cost About $200 Total Budget $2000

Project Milestones & Schedule

System Detailed Design Hardware platform Firmware program

Functional Decomposition 1. USB 3.0 to SATA adapter 2. Support for Mass-Storage Devices Compatible With the ATA/ATAPI-8 Specification 3. UASP protocol compliant mass storage device suitable for bridging hard disk drives (HDD) 4. Auto-load firmware (boot code and program we write)

System architecture Take the ARM cortex M3 microcontroller based USB 3.0 to SATA bridge board as an example. It provides various necessary firmware to implement bridging for hard drives, solid disk drives, optical drives and other SATA 3.0G standard drives. What we study is the connection between the host (USB 3.0 PC) and massive storage device, in super speed transfer mode.

ARM cortex M3 microcontroller structural diagram

Another USB 3.0 microcontroller SW6313 Single Chip USB 3.0 to SATA Bridge a product from Symwave (now part of SMSC)

Technical Support Symwave also provides a variety of host application Software Development Kits (SDK) for firmware update, Security password and Mass Production Tools - everything necessary for rapidly moving through development and into production. Ordering Information Design materials (schematics, layout, data sheet) are available upon request.

Transfer length (MSB 7, MSB 8) Firmware Program Principles on how the program works an example of a writing command block format WRITE(10) OP=2A   bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 Operation code byte 1 logical unit number reserved byte 2 logical block address byte 3 byte 4 byte 5 byte 6 byte 7 Transfer length (MSB 7, MSB 8) byte 8 byte 9 byte 10 byte 11

Some other SCSI command blocks Code Command 00 TEST UNIT READY (mandatory) 01 RECALIBRATE or REWIND 03 REQUEST SENSE (mandatory except RBC) 04 FORMAT UNIT 05 READ BLOCK LIMITS 07 REASSIGN BLOCKS INITIALIZE ELEMENT STATUS 08 READ (6) 0A WRITE (6) 0B SEEK (6) 28 READ (10) 29 READ GENERATION 2A WRITE (10)

An example routine void MSDWriteHandler() //check status, if or not successful { if(status) byte *adr; //The sector write failed byte flag; msd_csw.bCSWStatus=0x01; word i; dword sectorNum; WORD TransferLength; LBA.v[3]=gblCBW.CBWCB[2]; LBA.v[2]=gblCBW.CBWCB[3]; LBA.v[1]=gblCBW.CBWCB[4]; LBA._dword++; TransferLength._word--; LBA.v[0]=gblCBW.CBWCB[5]; if(TransferLength._word>0) TransferLength.v[1]=gblCBW.CBWCB[7]; TransferLength.v[0]=gblCBW.CBWCB[8]; check if more data to receive while(TransferLength._word>0) /* * Read data received from teh USB host and write the contents to the media else */ //all data received ... while(msd_csw.dcswDataResidue>0) MSDDataOut(); return; }

Testing plan Simulation: Writing code that will disable writing commands. We can do this process either in two ways: Simulating a writing error checking on the board Using the host to return valid parameter bits.

Testing Test Description Unit testing: Integration testing: Hardware blocking commands Return request of read operations No modification of requested information Error checking Integration testing: Develop a prototype of USB 3.0 that is integrated from USB 2.0 Big Storage capacity Faster transfer rate. Interface testing: Host to the blocker interface. Blocker to the Drive interface.

Metrics Faster Transfer rate: Time Delay: The device should have a higher transfer rate of up to 5Gbps. Time Delay: The device should have a shorter time delay between the input and output signals in order speed up the performance of the device

Basic building block implementations

Conclusion

Current Project Status Regular meetings with the client Analyzed project Decision on the direction for the project Built our group website and kept updating Market survey and contact with microcontroller companies in this field Completed documentation

Task Responsibility/Contributions Chen Zhao Project manager, System architect, developer, tester Elphas Sang Developer, tester Yan Fang Developer, tester, web master

Plans for the next semester Study on specific bridge chip and start programming Bridge chip simulation Systematic testing Keep a good documentation Present the final project including all deliverables to the client