Rutherford Appleton Laboratory Particle Physics Department A Novel CMOS Monolithic Active Pixel Sensor with Analog Signal Processing and 100% Fill factor J.P. Crooks 3, J.A. Ballin 1, P.D. Dauncey 1,A-M. Magnan 1, Y. Mikami 2, O. Miller 2,M. Noy 1, V. Rajovic 2, M. Stanitzki 3, K.D. Stefanov 3, R. Turchetta 3, M. Tyndel 3, E.GiulioVillani 3, N. K. Watson 2, J. A. Wilson 2 1 :Imperial College London, 2 :University of Birmingham, 3 : STFC Rutherford Appleton Laboratory   Pixels small enough: at most one particle/pixel   1-bit ADC/pixel: Digital ECAL   Example: ECAL – Terapixel APS for ILC SORMA West 2008 Berkeley, California USA   INMAPS process: Deep P-Well implant to shield N-Well housing readout electronic   Potential barrier between P ++ -Well and Epitaxial reflects back generated charge into the active layer   Dramatic improvement in charge collection New INMAPS process Pixel simulation standard process Detector Microphotograph and laser setup used for testing (right). Laser test results on INMAPS and NO INMPAS test pixel (left). Laser test results   Laser IR (1064nm, 2μm minimum shutter size, 4ns pulse)   Laser scans clearly indicate that the INMAPS process increases charge collection efficiency   Further investigations ongoing Source test results   Test with radioactive sources validate the usefulness of INMAPS process   Further tests ongoing to understand unexpected threshold spread   New sensor submission planned summer 08 Source test results: 55 Fe (right) and β source (left) on INMAPS test pixel INMAPS test results   Two different readout implemented at pixel level: Pre-shape and Pre-sample (160 and 189 transistors respectively)   Two different capacitor arrangements   DC power consumption approximately 10μW   0.18μm CMOS process ≈ 144mV ≈ 202mV ≈ 9.5μm   Study of optimal diodes location and size carried out on the new process   12μm epitaxial layer thickness Rst Vrs t Shape r PreRst Buffe r s.f Cfb Cin Buffe r s.f Vth+ Vth- Reset Sampl e Cstore Pream p Shap er Rst Cpr e Cfb Rfb Rin Cin Vth+ Vth- Pre-Shape Pixel Analog Front End Low gain / High Gain Comparator Pre-Sample Pixel Analog Front End Low gain / High Gain Comparator Hit Logic 150 ns 450 ns Hit Logic Self Reset Trim&Mas k SRAM SR Trim&Mas k SRAM SR Hit Output Pixel Readout Topology Analog   Each digital block serves 42 pixels from one row, split into groups of 6 pixels   After a hit, for each row the logic stores timestamp, pattern number and pattern in SRAM   pixels, approximatel6 8x10 6 transistors   1x1cm 2 total surface   Dead area 250μm / 2mm Pixel Readout Topology Digital INMAPS simulation results   In a complex pixel design a standard MAPS solution leads to low charge collection efficiency   Approximately 50% of the generated charge is collected by the readout N-Wells MAPS digital calorimeter concept Pixel collectionCharge (e - ) 87 Q max 362 Q min 1 5 Q stdev 107 Pixel collection Charge (e - ) 401 Q max 656 Q min Q stdev 95 Pre-shape (left) and pre-sample (right) pixel layout 50  50 μm 2 MAPS pixels SiD 16mm 2 area cells Contacts: