1 Background The latest video coding standard H.263 -> MPEG4 Part2 -> MPEG4 Part10/AVC Superior compression performance 50%-70% bitrate saving (H.264 v.s.MPEG-2) 25%-45% bitrate saving (H.264 v.s.MPEG-4) Target H.264 BP/MP video decoder for real-time HDTV (HD1080) applications Design Goals Low gate count Low internal SRAM requirement < 300K gates < 70K bytes

2 Techniques Reducing design complexity C Level algorithm optimization Hybrid block level pipeline control 4x4/16x16 block level Integrating Intra and inter functions Share the hardware cost High performance CABAC Decoder Look ahead scheme with cache register Reducing memory bandwidth Hybrid block level Motion Compensation Share the data and reduce memory access times Reducing internal SRAM Prediction Data Store Buffer (PDSB) Collect the data not used immediately and write them to external memory Reducing 98% of internal memory Reducing 48% of memory BW Reducing 40~60% complexity

3 Summary FPGA prototyping Chip implementation Technology TSMC 0.18  m CMOS 1P6M Supply Voltage1.8V Core Area2.9x2.9mm 2 Logic Gates160K (2-input NAND gate) SRAM4.5KB Decoding ToolsBaseline/Main Profile Operating Frequency 25MHz for D1 120MHz for HDTV1080 Power Consumption 65mW for D1 320mW for HDTV1080 Future direction Supporting H.264 High Profile (HP) video decoding Acknowledgements National Science Council (NSC) Chip Implementation Center (CIC) Taiwan Faraday Inc. of Taiwan Faraday FIE-8100 (Xilinx V2-4000)