LSST Electronics Review – BNL, January LSST Electronics Review BNL January Monitoring and Configuration R. Van Berg Electronics Mini-Review January 25 th, 2012

LSST Electronics Review – BNL, January Outline – Monitoring & Configuration Parameters measured Measurement cadence Signal conditioning and digitization Passing digitized data to CCS Special considerations for raft thermal control loop Serial bus for configuration and readback (protocol, topology, reset)

LSST Electronics Review – BNL, January Parameters Measured Voltages inside CABAC (clocks, biases, etc.) RTDs on CCDs RTDs on RSA RTDs on FEB Voltages on FEB through CABAC mux Voltages on BEB RTDs on BEB Others? For precision RTD measurement need a good four wire connection but this is not available on a single FEB! Need to jump back and forth betwixt the board pair. AD channel, low noise, low power, 24 bit  ADC w/ amp & reference via CABAC mux RTD connections On E2V CCD

LSST Electronics Review – BNL, January RTD AB RTD AB RTD AB RREF REFIN+REFIN- AIN- AIN+SDA SCK CS  ADC on BEB CABAC MUX B0 FEB-B CABAC MUX B2 CCD1 CCD0 CCD2 CABAC MUX B1 FEB-A Four Wire RTD Measurement using CABAC

LSST Electronics Review – BNL, January Measurement Cadence A  ADC like a AD7794 is relatively slow – “…up to 470 Hz update…” Nevertheless, with one per BEB that is a new reading every 355  s per RTM or for the whole focal plane one reading every 17  s (ignoring, for Vincent’s benefit, the corner rafts). However, there are other constraints on when we can change the configuration of what we are measuring –FEB SPI bus is single ended, changing configuration is potentially very noisy –Assume can only change FEB configuration during non-readout time –May not be able to (or want to) change during integration time –Should be no constraints during slew times or non-visit periods –BEB SPI (i.e. ADC configure and readout) is also single ended and could possibly impose similar constraints but would expect not SPI bus speed up to 5 MHz –Configuration registers up to 64 bits (most set up only ab initio) < 20  s

LSST Electronics Review – BNL, January Measurement Cadence – II – Possible Scheme Startup configuration of ADCs done at initial startup A visit – 1.At end of slew, configure each FEB to connect to ONE signal – e.g. FEB 1 – RTD on CCD 2 FEB 2 – RTD on RSA, position x FEB 3 – RTD on CCD 4 FEB 4 – RTD on RSA, position y FEB 5 – RTD on CCD9 FEB 6 – RTD on FEB position z 2.Read each temperature at a 10 Hz (??) rate during integration and readout 3.At start of slew run through all other voltage choices a few samples each Configure all FEB/BEB, read 10 (?) samples Repeat for next voltage 4.Each FEB/BEB set has less than 50 different sample points so ~ 1 second 5.Go to 1. but change CCDs for next visit

LSST Electronics Review – BNL, January Measurement Cadence – III – Possible Scheme Resulting data block for one visit –2x18 seconds worth of temp data on 3 (of 9) CCDs and 2 (of 4 or 6?) RSA RTDs at 10 Hz – so 2160 measurements (3 Bytes each) so ~ 10kB –10 readings of each parameter in RTM during 1 second of slew ~ 12kB

LSST Electronics Review – BNL, January Signal Conditioning & Digitization RTDs –A device like the AD7794 (Linear, Maxim and TI have similar) includes a current source and reference for doing a four wire measurement of the RTD – no other signal conditioning needed. Internal CABAC voltages –The CABAC will include voltage dividers to keep all voltages within range so, again – no other signal conditioning needed External voltages on FEB –Avoid active conditioning (to avoid adding more parts to qualify for cold) but simple voltage dividers with filters easy to provide (RTDs on FEB treated just as other RTDs, no conditioning needed External voltages on BEB (coming in through on-ADC mux) – voltage dividers with filters needed for larger voltages, a divider and inverter needed to measure substrate bias voltage (do we need to?), no obvious other conditioning needed but we may find something….

LSST Electronics Review – BNL, January Passing Digitized Data to CCS Meta-data accompanying image data –Natural place for slowly varying quantities or data only acquired once an image or once a visit Voltages Board temperatures Configuration data (e.g. timing code) Time of day for start of image data (based upon TCM stable clock) precision to 20ns Time of day for ADC measurements as desired (clock count at convert time) –Append to image data in bulk transfer (~ 300MB of image + ~ 10kB of meta data) can decide later in stream what pieces get saved to DB, get embedded in image file or get tossed Control data needed in “real time” – really only CCD and raft temperature data –Available in registers in RCM FPGA (ADC values and times) –Hardware path to CCS is via DAQ –CCS read of latest values as desired for control loop

LSST Electronics Review – BNL, January Control Control commands come from CCS into RCM via the DAQ hardware connection RCM FPGA turns commands (register settings) into SPI bus commands to: –CABAC for configuration of biases* –CABAC for monitoring mux configuration –ASPIC for gain etc. configuration* –BEB DACs for clock levels –BEB DACs for OD levels –BEB DACs for heater current(s) –* Initialization only

LSST Electronics Review – BNL, January Special considerations for raft thermal control loop Control loop stability and speed optimization depends on: –Precision and accuracy of temp measurements –Which temperatures are used for control and which heaters are used for makeup 9 CCD sensor temperatures N RSA sensors (up to 9 is natural in this architecture) M RSA heaters (up to 6 is natural – 1 per BEB drive) –How often temperatures are measured –Quality of model of thermal performance This design easily handles a nearly continuous, many tens of Hz, measurements of up to six RTDs Initial thermal models suggest thermal time constants of minutes or tens of minutes Need a greatly refined model to arrive at an optimal system but the available data bandwidth looks to have three or so orders of magnitude reserve over the likely Nyquist frequency

LSST Electronics Review – BNL, January Serial bus for configuration and readback (protocol, topology, reset) The bus planned for the CABAC and ASPIC is based upon SPI (a rather loose protocol definition!) but adding a fifth, “Load” wire to allow readback of stored data and an asynchronous override reset to ensure a well defined initial state Present RCM-BEB design has a single SPI bus with seven bits of address to produce up to 128 separate SS (slave select) lines to handle both commercial (ADC / DAC) devices and ASICs May want to provide multiple independent SPI buses in order to parallelize operations and speed reconfiguration – e.g. at the most extreme, a separate bus for each BEB and each FEB (but, obviously, with fewer address bits per bus)

LSST Electronics Review – BNL, January Summary Control and monitoring of an RTM by the CCS is via local SPI bus(es) within a raft where communication between CCS and the RCM hardware is carried over a separate channel of the high speed DAQ physical connection Multiple temperatures and voltages can be monitored on each board of the RTM –List of monitored voltages and temperatures is extensive but maybe not final –No immediate plan to do any analog monitoring of the RCM itself, but one more ADC with mux would enable monitoring RCM local voltages and temperatures if that proves useful Monitoring rates are relatively slow (10’s – 100’s of Hz) but fast compared with expected time constants for control loops The planned interface is compatible with commercial devices as well as the custom ASICs (simulation and layout complete for the CABAC)

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