CCD Clocking and Biasing CABAC_0 : Design Test_0 : Design Pierre Antilogus (from a Hervé Lebbolo’s talk) BNL, Raft Electronic Workshop January 25 th 2012

CABAC : clock and biases asic for CCD 2 IΦ0IΦ1IΦ2IΦ3IΦ0IΦ1IΦ2IΦ3 IΦ3IΦ3 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

3 CCD requirements OD &Biasese2v CCD250ITL/STA1920AHPK S exposereadouterase Back substrateBS-70BB-10VBB50300,2 Front substrateFS0SUB0VGR000 GuardGD30SC Output DrainVOD30OD27VOD Output GateVOG2OG-2VOG-5 Reset DrainVRD18RD15VRD Test inject source----VISV Test injectgate----VIGV000 ClocksHILOHILOHILO erase Parallel Serial100, Reset Gate Summing Well Transfer Gate Capacitances (estimated) Parallel per phase64nFunavailable25nF(2K x 1K device) Serial per phase320pFunavailable50pF RGunavailable 10pF SW----10pF TG pF baseline H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

CABAC requirements OD and Biases: – 2 OD : 8 bit programmable level, 16 mA capability each, exposure&readout levels, load : 10Ω + 10µF, out level 13 to 36V – 1 RD : 8 bit programmable level, 1kΩ +.1µF load, out level 13 to 36V – 1 GD : 8 bit programmable level, 1kΩ +.1µF load, out level 13 to 36V – 1 OG : 8 bit programmable level, 1kΩ +.1µF load, out level 100mV to 4.8V – 1 spare0 : 8 bit programmable level, 1kΩ +.1µF load, out level 13 to 36V – 1 spare1 : 8 bit programmable level, 1kΩ +.1µF load, out level 100mV to 4.8V Clocks : – 4 parallel, 8 bit programmable current capability (max 300mA), common voltage rails (ΔV = 20V max), exposure/readout modes (static current divided by 10) – 4 serial, 8 bit programmable current capability (max 16mA), 2 voltage rails (3+1) (max 20V), exposure/readout modes H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop 4

CABAC requirements Readout & Exposure modes input independant from serial programing Temperature sensor (current source + diode connected mos transistor) Multiplexor : Possibility to output 2 of any signal provided by CABAC or external input for monitoring, output can be disabled for paralleling Operates at 173K Programmation by serial link with read back & asynchronous reset H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop 5

Process Process : AMS CMOS 0.35µm 50V, H35B4D3 Care has to be taken on Vgs for lifetime (LTacc) : lifetime = 10 years/LTacc Cryo temp lifetime : no guarantee from AMS CABAC_0 qualification tests will address the lifetime risk If needed the CABAC / front end could be higher than - 100°C H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop 6

Pincount (Ver Dec 2011) 7 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

CABAC simplified synoptic 8 CABAC Serial link RO EXT Clocks OD Biases Muxout Clocks timing H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

9 8 bit DACVCCS Current mirror Current mirror LVDS receiver Level translator Clock Switch VDD upper VDD lower Current setting LVDS clock Clocks RO VDD command Clock

Clock layout 10 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

Clock Sim 11 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

Clock Sim 12 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

Clock load 13 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

14 OD Voltage Amplifier VDD upper OD Readout setting register RO 8 bit DAC Exposure setting register VDD lower

OD Sim 15 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

OD Sim (nap mode) 16 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshopH. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop 17 Biases Voltage Amplifier VDD H or L Bias setting 8 bit DAC

H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshopH. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop 18 4:1 Mux OD, RD, OG 4:1 Mux GD, Spare, Ext, Ext 4:1 MuxSerial, RG 4:1 MuxParallel 4:1 Mux OD, Ext 4:1 Mux Temp, Spare, Ext, Ext 4:1 MuxSerial, RG 4:1 MuxParallel 4:1 Mux Out 0 Out 1 Dual 16 to 1 multiplexer

Mux Sim 19 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

Temperature & Test H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshopH. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop 20 Buffer Vdd BBias Current Mirror Temp Test Gnd

H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshopH. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop 21 Programmation Write and read back (5 wires) + asynchronous reset (Version Nov 2011) sclk mosi ss sclk ss 0 1 … sclk ss 144 To DAC’s miso sclk rb sclk rb 0 1 load … sclk rb 144 load ss AND rb mosi

22 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop Serial link : Place & Route ~570*570µm²

Dec Full Cabac_0 layout 23 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop Area : ~36mm²

Status as Dec 2011 CABAC_0 not submitted this fall : – Too many DRC errors not understood – Not all simulations had been performed – Price : ~40k€ – A few change in design foreseen Decision to send a smaller circuit for tests purpose : Test_0 Submission : after Test_0 preliminary tests (2012/04/24) H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop 24

TEST_0 AMS HV CMOS chip for HV & Cold tests purpose 5 mos transistors : 1 large (5000*3) 20V thick oxyde Pmos 1 large (5000*2) 20V thick oxyde isolated Nmos 1 (100*3) 20V thin oxyde Pmos 1 (100*2.5) 20V thin oxyde isolated Nmos 1 (100*3) 50V thick oxyde Nmos One high level bias with 8 bit DAC One temp sensor 25 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

TEST_0 layout 26 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop Area : 5.4mm² 10 chips packaged in QFN36 15 naked dies Sent early november Delivry expected in february

CABAC : work under way & Plan CABAC design change since November 2011 Version : –Passive mux for all signals except clocks –Electronic calibration pulser (pulse on RD, see diagnostic talk) –Upgrade the serial link, to achieve “multi daisy chain “ : goal have the possibility to build as many daisy chains as wanted, goal : chain 1 CABAC (first) and 1 ASPIC (last) in a single daisy chain (to reduce the impact of chip failure) TEST_0 and SCC characterization (see talk Thursday ) : –TEST_0 should be characterized before CABAC_0 submission Working plan : –Work on the CABAC implementation resumed since a week (mid-Jan 2012) –CABAC implementation should be finalized as if we were submitting the chip in February –CABAC chip design will be review mid-March 2012 (camera workshop) –Submission : 24 May 2012 ( as test on TEST_0 completed) 27 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

CABAC Electronic Calibration Pulser, Possible implementation : 8 bit DAC Pulser CCD trig To aspic Reset RD calib pulse

CABAC SPI double daisy chain simulation Chip 2 Chip 1 MISO MOSI MASTER Chip 4 Chip 3 MISO MOSI SS 1SS 2 aclr clk rb MOSI MISO

1 st solution three state output buffer Chip 2 Chip 1 MASTER Chip 4 Chip 3 miso ss miso MISO MOSI MISO MOSI

2 nd solution open drain output buffer Chip 2 Chip 1 MASTER Chip 4 Chip 3 miso Broadcast allowed MISO MOSI MISO MOSI

End of Presentation

Clock scheme 33 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

Clocks scheme 34 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

OD Scheme 35 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

Low level Bias scheme 36 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

High level bias 37 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

Mux scheme 38 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop

Temp & Test scheme 39 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic workshop