J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Flip Chip/Bumping Process at VTT Last modified March 16, 2007 By Jaakko Salonen

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 VTT's Flip Chip Process: Overview

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Flip Chip Bonding With Solder Bumps Solder bumping is done by electroplating for whole wafers. The wafers are then diced, and the individual chips are flip chip bonded together. Typical bump diameter: um Typical bump pitch: um Bump/pixel count per ROC: ~2, ,000 Sensor chip, typically hi-res (1 1 1) silicon. Readout chips, 0.25-um CMOS, typically 1 to 10 ROC’s per sensor chip. Area array type interconnecting technology is ideal for hybridizing pixel sensors with readout chips.

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Main Process Steps 1. Incoming Inspection & Wafer Cleaning. 2.Sputtering of Field Metals. 3. Photolithography Step. 4.Electroplating of UBM & Solder. 5.Stripping of Photoresist. 6.Etching of Field Metal Etching of Field Metal Solder Reflow. 9. Thinning of Readout Wafers (optional). 10.Dicing. 11.Flip Chip Bonding. Steps marked in red are done in a Class-10 clean room. Steps marked in blue are done in a Class 10,000 clean room.

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Flip Chip Hybridization 1(4) Readout IC wafer Sensor wafer Sensor & Readout wafers

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Readout IC wafer Sensor wafer Bumping process (at wafer level) Solderable pads Solder bumps Flip Chip Hybridization 2(4)

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Readout IC wafer Detector wafer Dicing & chip pick-up Flip Chip Hybridization 3(4)

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Flip chip bonding (chip-by-chip) Hybridized sensor/readout (detector) assembly Sensor & readout chips Flip Chip Hybridization 4(4) Sensor chip Readout chip Sensor chip

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 VTT's Flip Chip Process: Step by Step

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Bumping Process

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Incoming Inspection Zeiss Axiotron 2 Microscope Dirt particle on customer's readout wafer Visual incoming inspection of wafers is done before bumping process. After inspection, wafers are cleaned using liquid solvents and ultrasound.

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Sputtering of Field Metals Sputtered Ti-W/Cu (40 nm/700 nm) layer is used as field metal for electroplating. Light in situ sputter etching step is used to remove native oxide from Al contact pads. Von Ardenne CS730S is used for 4", 5", and 6" wafers. TEL Eclipse Mk. IV is used for 8" wafers. Von Ardenne CS730S Sputterer TEL Eclipse Mk. IV Sputterer

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007Photolithography Patterned 18-  m thick photoresist is used to define the bump sites on the wafers. Suss MicroTEC ACS200 Automated Coating System is used to coat wafers with photoresist. Suss MicroTEC MA6 Mask Aligner is used to expose 4", 5", and 6" wafers. Suss MicroTEC MA200 Mask Aligner is used to expose 8" wafers. Suss MA200 & MA6 Mask Aligners Suss ACS200 PR coating system

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007Electroplating Nickel is first electroplated in the holes in the photoresist Solder is then electroplated on top of the nickel. Essentially the same process is used for both the sensor and the readout side; only the volume of the solder is different. Wet bench for electroplating Wafer holder for electroplating

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Stripping of Photoresist After electroplating, photoresist is stripped away using solvents and ultrasound on automated wet bench.

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Etching of Field Metals The field metals, which short-circuited the bump sites to one another during electroplating, are removed by wet etching.

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Solder Reflow ATV SRO-704 Reflow Oven Bumps after reflow ATV SRO-704 Reflow Oven is used for solder bump reflow. Formic acid ambient reduces oxides on bump surfaces.

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Wafer Thinning Strasbaugh 7AF Back Grinder Strasbaugh 6DS-SP CMP Strasbaugh 7AF Intelligent Grinder is used for back grinding. Strasbaugh 6DS-SP CMP Planarizer is used for CMP polishing. A layer of protective tape is used to protect the bumps and the front side of the wafer. 200 mm Si wafer back ground & polished to thickness of 150  m

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007Dicing Disco DFD651 Dicing Saw DFD651 in action Disco DFD651 Dicing Saw is used for dicing. Wafers are laminated on tape/ tape frames for dicing

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Flip Chip Bonding Suss FC150 Flip Chip Bonders Close-up of bonded chips Flip chip [tack] bonding is performed on two Suss MicroTEC FC150 Flip Chip Bonders. A post-tack bonding 'assembly reflow' for self-alignment is done in the ATV SRO-704 Reflow Oven in a formic acid ambient. Suss FC150 in use

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Summary

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Summary An overview of VTT's flip chip process was given. Electroplating is used to deposit solder on wafers at sites defined by photoresist. Readout wafers can be optionally thinned after bumping. All process steps are performed in house. 4", 5", 6", and 8" wafers can be processed.

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 The End. Thank you for your attention. VTT Technical Research Centre of Finland Tietotie 3, Otaniemi, Espoo, Finland