InputsMetricsCode

MAIN MEMORY core Interconnection network Private data (LI) cache Cache controller core Cache controller Private data (LI) cache MULTICORE PROCESSOR CHIP InputsMetricsCode

Name#coresC Latency M Latency M Blocks Cache Blocks Input Size Store % Number of invalidate messages in MSI and MESI Number of write-backs in MSI and MOSI L K1K 0 L K1K 40 L K1K 80 M K1K10K0 M K1K10K40 M K1K10K80 H K1K100K0 H K1K100K40 H K1K100K80 InputsMetricsCode

Name#coresC Latency M Latency M Blocks Cache Blocks Input Size Store % Sensitivity of write-backs to the cache size MC K1010K50 MC K10010K50 MC K1K10K50 Sensitivity of write-backs to the # of cores MW K10010K50 MW K10010K50 MW K10010K50 InputsMetricsCode  Goals: number of invalidate messages (MESI), number of write backs (MOSI)

InputsMetricsCode

InputsMetricsCode

InputsMetricsCode

InputsMetricsCode

InputsMetricsCode

InputsMetricsCode

InputsMetricsCode

 [1] - Daniel J. S. Mark D. H. David A. W., “A Primer on Memory Consistency and Cache Coherence,” Morgan Claypool Publishers,  [2] – Suleman, Linda Bigelow Veynu Narasiman Aater. "An Evaluation of Snoop- Based Cache Coherence Protocols."  [3] – Tiwari, Anoop. Performance comparison of cache coherence protocol on multi-core architecture. Diss  [4] – Chang, Mu-Tien, Shih-Lien Lu, and Bruce Jacob. "Impact of Cache Coherence Protocols on the Power Consumption of STT-RAM-Based LLC."  [5] – CMU : Parallel Architecture and Programming. Lecture Series. Spring 2012