Printed Electronics SolidState Technology. Progress in Printed Electronics: An Interview with PARC’s Janos Veres. 2012 Alec Roelke, Tom Tracy II ECE 6332.

Slides:



Advertisements
Similar presentations
CESG, Fall 2011, 5 th November 2011 Stuart Fowell, SciSys Device Virtualisation and Electronic Data Sheets.
Advertisements

Chapter 2 Modern CMOS technology
Snapback avoidance design flow for a memory technology
Circuit Extraction 1 Outline –What is Circuit Extraction? –Why Circuit Extraction? –Circuit Extraction Algorithms Goal –Understand Extraction problem –Understand.
OctoTools™ JBM Systems, Inc 4 Bald Hill Lane Peabody, MA
New Features in Sonnet ® 7.0 Planar Electromagnetic Analysis A New Benchmark in Capability by James C. Rautio Sonnet Software, Inc.
Analog VLSI Design Nguyen Cao Qui.
Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver VLSI Design Using PC-Based Tools Cherrice Traver Union College Schenectady,
Ch.3 Overview of Standard Cell Design
© 2011 Adobe Systems Incorporated. All Rights Reserved. Adobe Confidential. Kiran Kaja | Accessibility Engineer Ensuring Accessibility in Document Conversion.
CADENCE Chintan Trehan 06/27/06. IC Design Flow System-Level Design Circuit-Level Design Physical level Design Layout verification Submit to Foundry Device.
MIS 5241 SOFTWARE. MIS 5242 Agenda The Stored Program Concept Software as Control Software as Simulation.
February 25, 2009Chaitanya: MEE Project Defense1 Fully configurable hierarchical transaction level verifier for functional verification Master’s Defense.
Physical Design Outline –What is Physical Design –Design Methods –Design Styles –Analysis and Verification Goal –Understand physical design topics Reading.
Project 2: Cadence Help Fall 2005 EE 141 Ke Lu. Design Phase Estimate delay using stage effort. Example: 8 bit ripple adder driving a final load of 16.
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) lecture06 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008.
Overview of Program Features. Progress to Date  Discussed with DSS what they want accomplished  Broke tasks down into phases  Completed phase 1 based.
1 GPS Waypoint Navigation Team M-2: Charles Norman (M2-1) Julio Segundo (M2-2) Nan Li (M2-3) Shanshan Ma (M2-4) Design Manager: Zack Menegakis Presentation.
[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Nov. 11 Overall Project Objective : Dynamic Control.
VLSI Lab References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially.
Open hardware and unconventional electronics John Sarik Columbia University
N A managed approach to planning and controlling the implementation of complex application software. n A flexible tool kit, designed to support the Project.
Organic Electronics Yousof Mortazavi VLSI Course Presentation December 2004.
Trimble Connected Community
MCTS GUIDE TO MICROSOFT WINDOWS 7 Chapter 9 User Productivity Tools.
© 2005 IBM Corporation IBM Printing Systems IBM OUTPUT ENVIRONMENT IPPD How workflow techniques can by implemented using IPPD Simon Jones 14 th September.
Unleash PDK with Open Standards Synopsys 18th EDA Interoperability Developers' Forum Hau-Yung Chen Nov. 9, 2006 Synopsys 18th EDA Interoperability Developers'
® Copyright 2010 Adobe Systems Incorporated. All rights reserved. ® ® 1 INTRODUCTION TO ADOBE FLASH PROFESSIONAL CS5.
MEMSCAP/Mentor Graphics MEMS Solution: A Partnership Model Major Features: Mixed Technology Solution MEMS Intellectual Properties Access to MEMSCAP expertise.
EEE 348E INTRODUCTION TO IC DESIGN P.M Dr Othman Sidek (Director of CEDEC) Mr. Arjuna Marzuki (room 2.15, ext: 6021) Instructor/Tutor.
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Xilinx Design Flow FPGA Design Flow Workshop.
CMP 4202: VLSI System Design Lecturer: Geofrey Bakkabulindi
© Copyright 2003 Nassda Corporation OpenAccess 2.0 — A Nassda Perspective Graham Bell, Director of Marketing.
Data Management Console Synonym Editor
Chonnam national university VLSI Lab 8.4 Block Integration for Hard Macros The process of integrating the subblocks into the macro.
PRESENTED BY, SARANYA , GAYATHRI, II ECE-B.
Organic Electronics Presented By: Mehrdad Najibi Class Presentation for Advanced VLSI Course.
Lecture #2 Page 1 ECE 4110– Sequential Logic Design Lecture #2 Agenda 1.Logic Design Tools Announcements 1.n/a.
Elucidative Programming Kurt Nørmark Aalborg University Denmark SIGDOC September 2000.
Electronic Parts.
Esri UC2013. Technical Workshop. Technical Workshop 2013 Esri International User Conference July 8–12, 2013 | San Diego, California Supporting High-Quality.
CADENCE CONFIDENTIAL 1CADENCE DESIGN SYSTEMS, INC. Cadence Front to Back End Adil Sarwar March 2004.
Chapter2 Networking Fundamentals
GTK - TDC analysis Lukas Perktold 14 th April 2010.
Pico-Sec Simulation Workshop University of Chicago 12/12/06 Simulating Front-end Electronics and Integration with End-to-end Simulation Fukun Tang Enrico.
CS/CAPP AUTOMATED TESTING PROGRAM Senior Design III Jeff Williams Bekah Michael.
07/10/2007 VDCT Status Update EPICS Collaboration, October 2007 Knoxville, Tennessee
Implementation of a Relational Database as an Aid to Automatic Target Recognition Christopher C. Frost Computer Science Mentor: Steven Vanstone.
© 2005, it - instituto de telecomunicações. Todos os direitos reservados. Tools and Methods to Assist Analog IC Designers Nuno Horta, PhD Head of Integrated.
Monday, February 14, Agenda: 1.Top level system design using ADS New Budget analysis 2.Modeling “off the shelf components” In terms of data based.
Full-Wave (Bridge) Rectifier
A computer contains two major sets of tools, software and hardware. Software is generally divided into Systems software and Applications software. Systems.
GlueX Collaboration May05 C. Cuevas 1 Topics: Infrastructure Update New Developments EECAD & Modeling Tools Flash ADC VXS – Crates GlueX Electronics Workshop.
OLEDs Theory & Fabrication
3D Design IPHC Frédéric Morel - Grégory Bertolone - Claude Colledani.
SENSITIVE SKIN. OUTLINE INTRODUCTION SKIN MATERIALS DEVICES SIGNAL PROCESSING ADVANTAGES DISADVANTAGES APPLICATION CONCLUSION.
Jean-Marie Bussat/Patrick Pangaud – July 9, FPPA design methodology  Intersil methodology  FPPA design constraints  "Symbolic" versus "Full" 
EMT 351/4 DIGITAL IC DESIGN Week # 1 EDA & HDL.
OLEDs Theory & Fabrication
Programmable Hardware: Hardware or Software?
HW5: Mentor Graphics I “ Design of a CMOS Inverter”
TRANSLATORS AND IDEs Key Revision Points.
EE 584 Homework #1 Inverter Design
Solution-Processed Indium Oxide Transistors: Printing Two-Dimensional Metals UMN MRSEC Award DMR# Dan Frisbie & Chris Leighton (IRG-1), University.
Matlab as a Development Environment for FPGA Design
Network Analysis using Python
CHIP DESIGNING GROUP MEMBERS :- Varunavi Neharika Daksh Anubhav
2A8 DRC with Deep Networks
Computer-Aided Design (CAD)
Presentation transcript:

Printed Electronics SolidState Technology. Progress in Printed Electronics: An Interview with PARC’s Janos Veres Alec Roelke, Tom Tracy II ECE 6332 Fall 2012

Why Printed Electronics? Can be printed with an inkjet printer Use organic materials instead of silicon Many different substrates (flexible) Much cheaper than silicon process Much faster to prototype Applications o Wearable electronics o Flexible antennas/displays o Materials/Electronics printing hybrid

Design Flow Update Design Kit Add Layers Add Devices Design Rules Model Layout Layout to Bitmap Schematic DRC LVS Simulation Manual Layout to Bitmap Print

Problem Statement Printed electronics still lacks a standardized design flow. There are several competing printer manufacturers selling design kits and materials that are meant to only be used with their hardware. This makes collaboration and experimental replication difficult. Solution Statement Develop a configurable design flow for the design, simulation, verification, and printing of printed electronics that is meant to work with all printing materials and printers.

OPDK: Organic Process Design Kit Created by University of Minnesota's Wei Zhang, Ph.D Design of printable Organic Thin Film Transistors (OTFTs) Devices o PTFT_P3HT_TG: Top-Gated P-type OTFT o TFT_CNT_TG: Top-Gated Pass TFT o Resistor o Capacitor W. Zhang. University of Minnesota VLSI Group. The Organic Process Design Kit (OPDK) N-Type TFT? :(

Developing a Configurable Design Flow Add new materials Add new devices Add design rules Conversion to printable format

Adding New Materials Materials are represented as layers in Cadence Layers are stored in the techfile Use DEFT to edit the OPDK techfile o Add layer name, display properties, priority

Adding New Devices Devices are stored in databases by Cadence The databases contain information about: o sizes o associated layers o parameters (for PCell) o model Edit LVS

Simulation Added n-type layer and created NTFT_BBL_TG device Added model for device. Created inverter schematic and simulated

Adding Design Rules Define process rules about layer arrangement Entirely manual Created DRC editor that parses the file and provides editor interface

Layout to Bitmap Printer manufacturers provide proprietary tools Francesc Vila Garcia developed a Layout2Bitmap tool that converts GDSII to bitmap Waiting on licensing

Future Work Collaborate with Garcia and TDK4PE coalition Automate o Layer addition o Device creation o Rules configuration

Conclusion Created tutorials to configure PDK Created DRC tool to simplify editing design rules Extended OPDK with N-type OTFT Collaborating with international group