© Copyright 2009 Xilinx Copyright 2012 Xilinx August 2012 Zynq-7000 All Programmable SoC Product Overview The SW, HW and IO Programmable Platform

Copyright 2012 Xilinx Breakthrough Processing Platform –Higher system performance, lower total power –Flexible and scalable solution Industry Standard Design Environments –Well defined SW programming model –Familiar SW & HW design flows Flexible Accelerators and IP –World class 28nm unified Programmable Logic –Standard AMBA ® 4 AXI interfaces Broad Ecosystem Support –Tools, OS’s & IPs –Middleware, codecs –System integrators and training partners. Page 2 Introducing the Zynq™-7000 All Programmable SoC Familiar Processing System + Scalable Programmable Logic

Copyright 2012 Xilinx Next level of Programmable System Integration –All programmable (Hardware and Software) processing platform –ARM Cortex™-A9 MPCore™ Processing System with hardened peripherals, ADC and 28nm scalable optimized programmable logic Increased System Performance –1 GHz, dual core processors with NEON and vector floating point units –7 series programmable logic (PL) with built-in DSP –High bandwidth, low latency connects enable acceleration of key functions BOM Cost Advantage in an cost optimized 28nm platform –Integration for component reduction, PCB simplification and area reduction –Platform approach enables aggregation of volumes over several projects Low Total Power solution –Industry-leading ARM processors maximize MHz/W and low power states –28nm HPL process and Integration provides ultra-lower power data transfers –Software and Hardware programmable power control and operating modes Accelerated Design Productivity for TTM and TIM advantage –Industry standard HW and SW development tools for fast Time-To-Market –Flexible and scalable platform enables extended Time-In-Market –Extensive ecosystem of tools and solutions partners Page 3 Value of the Zynq-7000 All Programmable SoC

Copyright 2012 Xilinx Complete ARM®-based Processing System –Dual ARM Cortex™-A9 MPCore™, processor centric –Integrated memory controllers & peripherals –Fully autonomous to the Programmable Logic Tightly Integrated Programmable Logic –Used to extend Processing System –High performance ARM AXI interfaces –Scalable density and performance Flexible Array of I/O –Wide range of external multi-standard I/O –High performance integrated serial transceivers –Analog-to-Digital Converter inputs Page 4 Zynq-7000 Family Highlights Software & Hardware & IO Programmable 7 Series Programmable Logic Common Peripherals Custom Peripherals Common Accelerators Custom Accelerators Common Peripherals Processing System Memory Interfaces ARM ® Dual Cortex-A9 MPCore™ System

Copyright 2012 Xilinx AMBA Open Standard Interconnect  High bandwidth interconnect between Processing System and Programmable Logic  ACP port for enhanced hardware acceleration and cache coherency for additional soft processors AMBA Open Standard Interconnect  High bandwidth interconnect between Processing System and Programmable Logic  ACP port for enhanced hardware acceleration and cache coherency for additional soft processors Page 5 Complete ARM-based Processing System Processing System Ready to Program Integrated Memory Mapped Peripherals  2x USB 2.0 (OTG) w/DMA  2x Tri-mode Gigabit Ethernet w/DMA  2x SD/SDIO w/DMA  2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 32b GPIO Integrated Memory Mapped Peripherals  2x USB 2.0 (OTG) w/DMA  2x Tri-mode Gigabit Ethernet w/DMA  2x SD/SDIO w/DMA  2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 32b GPIO Processor Core Complex  Dual ARM Cortex-A9 MPCore with NEON™ extensions  Single / Double Precision Floating Point support  Up to 1 GHz operation Processor Core Complex  Dual ARM Cortex-A9 MPCore with NEON™ extensions  Single / Double Precision Floating Point support  Up to 1 GHz operation High BW Memory  Internal –L1 Cache – 32KB/32KB (per Core) –L2 Cache – 512KB Unified  On-Chip Memory of 256KB  Integrated Memory Controllers (DDR3, DDR2, LPDDR2, 2xQSPI, NOR, NAND Flash) High BW Memory  Internal –L1 Cache – 32KB/32KB (per Core) –L2 Cache – 512KB Unified  On-Chip Memory of 256KB  Integrated Memory Controllers (DDR3, DDR2, LPDDR2, 2xQSPI, NOR, NAND Flash)

Copyright 2012 Xilinx On-Chip Memory (OCM) –Dual-ported 256KB –Low-latency CPU access –Accessible by DMAs, Programmable Logic, etc. Powerful Application Processor at Heart The Application Processor Unit (APU) Page 6 MI O NEON™/ FPU Engine Cortex™-A9 MPCore™ 32/32 KB I/D Caches NEON™/ FPU Engine Cortex™-A9 MPCore™ 32/32 KB I/D Caches 512KB L2 Cache Snoop Control Unit 256 KB OCM Interrupt Controller, Timers, DMA, Debug, etc. Dual ARM Cortex-A9 MPCore with NEON extensions –Up to 1 GHz operation (7030 & 7045) –2.5 DMIPS/MHz per core –Multi-issue (up to 4), Out-of-order, Speculative –Separate 32KB Instruction and Data Caches with Parity Snoop Control Unit –L1 Cache Snoop Control Snoop filtering monitors cache traffic Accelerator Coherency Port Level 2 Cache and Controller –Shared 512 KB Cache with parity –Lockable

Copyright 2012 Xilinx DDR controller –DDR3, DDR2, and LPDDR2 –16 bit or 32 bit wide; ECC on 16 bit up to DDR1333 up to DDR800 up to DDR800 –73 dedicated DDR pins NAND Controller –ECC –8 bit or 16 bit data widths NOR/SRAM Controller –8 bit data width Quad SPI (QSPI) Controller –Up to 2 QSPI parallel memories for high- speed boot and configuration Processing System External Memories Built-in Controllers and dedicated DDR Pins 32 bit16 bit 4 x 8 bit2 x 8 bit 2 x 16 bit1 x 16 bit 1x 32bitNA NAND CTRL NOR /SRAM CTRL QSPI CTRL To MIO 2 Chip Selects APU DDR Controller Legend Arrow direction shows control, Data flows both directions AXI3 64 bit / APB 32 bit From L2 Cache Controller From Central Interconnect 2 Dedicated to Programmable Logic Page 7

Copyright 2012 Xilinx Two USB 2.0 OTG/Device/Host Two Tri- Mode GigE (10/100/1000) Two SD/SDIO interfaces Two CAN 2.0B, SPI, I2C, UART Four GPIO 32bit Blocks Multiplexed Input/Output (MIO) –Multiplexed output of peripheral and static memories –Two I/O Banks: each selectable - 1.8V, 2.5V or 3.3V –Configured using new feature in XPS Extended MIO –Enables use of Select IO with PS peripherals Comprehensive set of Built-in Peripherals Enabling a wide set of IO functions 2x GigE with DMA 2x USB with DMA 2x SD/SDIO with DMA I/O MUX 2x SPI 2x I2C 2x CAN 2x UART GPIO Extended MIO 54 Static Memory Controllers Page 8

Copyright 2012 Xilinx Programmable Logic to Memory –2 Ports to DDR Controller –1 Port to OCM SRAM Central Interconnect –Crossbar switches for high bandwidth communications –Processing System Master Ports 2x 32b AXI Ports from Processing System to Programmable Logic Connects CPU Block to Common Peripherals, through the Central Interconnect –Processing System Slave Ports 2x 32b AXI Ports from Programmable Logic to Processing System ACP (Accelerator Coherence Port) –Low-latency cache-coherent port for programmable logic Enables application-specific customizations with a standard programming model Page 9 Primary System Interconnects Maximizing Data Transfers Legend Configurable AXI3 32 bit/64 bit AXI3 64 bit / AXI3 32 bit / AHB 32 bit / APB 32 bit DDR Controller Programmable Logic to Memory OCM Arrow direction shows control, Data flows both directions... NAND, NOR/SRAM, QSPI Controllers Peripherals L2 Cache DMA Master/Slave AXI Interfaces to Programmable Logic Central Interconnect OCM APU ACP

Copyright 2012 Xilinx Page 10 Tightly Integrated Programmable Logic Scalable Density and Performance Integrated Analog Capability  Dual multi channel 12-bit A/D converter  Up to 1Msps Integrated Analog Capability  Dual multi channel 12-bit A/D converter  Up to 1Msps Over 3000 Internal Interconnects  Up to ~100Gb of BW  Memory-mapped interfaces Over 3000 Internal Interconnects  Up to ~100Gb of BW  Memory-mapped interfaces Built with State-of-the-art 7 Series Programmable Logic  Artix-7 & Kintex-7 FPGA Fabric  28K-350K logic cells  430K-5.2M equivalent ASIC gates Note: ASIC equivalent gates based on analysis over broad range of designs Built with State-of-the-art 7 Series Programmable Logic  Artix-7 & Kintex-7 FPGA Fabric  28K-350K logic cells  430K-5.2M equivalent ASIC gates Note: ASIC equivalent gates based on analysis over broad range of designs Enables Massive Parallel Processing  Up to 900 DSP blocks delivering over 1334 GMACs Enables Massive Parallel Processing  Up to 900 DSP blocks delivering over 1334 GMACs

Copyright 2012 Xilinx Page 11 Flexible External I/O Flexibility Beyond Any Standard Processing Offering 73 Dedicated Memory I/Os  DDR3 / DDR2 / LPDDR2 Memory Interfaces  Configurable as 16bit or 32bit 73 Dedicated Memory I/Os  DDR3 / DDR2 / LPDDR2 Memory Interfaces  Configurable as 16bit or 32bit 54 Dedicated Peripheral I/Os  Supports integrated peripherals  Static memory (NAND, NOR, QSPI)  More I/Os available though the Programmable Logic 54 Dedicated Peripheral I/Os  Supports integrated peripherals  Static memory (NAND, NOR, QSPI)  More I/Os available though the Programmable Logic High Performance Integrated Serial Tranceivers (Two largest devices only)  Up to 16 transceivers  Operates up to 12.5Gbs  Supports popular protocols  Integrated PCIe Gen2 block High Performance Integrated Serial Tranceivers (Two largest devices only)  Up to 16 transceivers  Operates up to 12.5Gbs  Supports popular protocols  Integrated PCIe Gen2 block Over 350 Multi-Standard and High Performance I/O  Up to V capable multi-standard I/O  Up to 150 high performance I/O  Up to differential 17 ADC inputs Over 350 Multi-Standard and High Performance I/O  Up to V capable multi-standard I/O  Up to 150 high performance I/O  Up to differential 17 ADC inputs

Copyright 2012 Xilinx Page 12 Zynq-7000 Device Portfolio Summary Scalable platform offers easy migration between devices

Copyright 2012 Xilinx BOM Cost Reduction Reduced Devices per Board –Processors, PLDs, DSPs –A/D converters –Power supplies, fans, etc… Reduced PCB Complexity –Fewer traces/interconnect/layers –Fewer power supplies –Smaller overall PCB In-System Reconfiguration Combines Multiple Device Functions –Reconfigureable programmable logic to provide specific functionality at a given time PS Aggregates Numerous IP Royalties for Net Cost Benefit –ASIC or full FPGA solutions would require purchase of these IPs from 3 rd parties. Platform approach enables higher volumes and lower prices Up to 40% BOM Cost Reduction vs. Multi- Chip Solutions

Copyright 2012 Xilinx Total Power Reduction Flexible/Tunable Power Envelope –Adjustable processor speed –Adjustable ARM AMBA®- AXI & memory speeds –ARM low power states –Programmable logic can be turned off –Programmable logic clock gating –Partial reconfiguration to reduce Programmable logic requirement Integration Power Reduction –Reduced interconnections between devices –Fewer system devices –Lower programmable logic power (28nm HPL process) Up to 50% Lower Power Vs. Multi-Chip Solutions Up to 50% Lower Power Vs. Multi-Chip Solutions Significant Power Reduction at the System Level

Copyright 2012 Xilinx Accelerated Design Productivity Reduced Time To Market –Fixed processor system with large set of built in peripherals –Xilinx standardizing on AMBA-4 AXI enhances portability of IPs –Scalable optimized architecture for IP re-use; AXI interfaces for plug & play IP –Accelerate development with targeted design platforms Increased Time In Market –Software and hardware re-programmability –Field upgradable –Address Processor/ASSPs short shelf life Dev.Dev. Design #1 Platform #1 Platform #1 Dev.Dev. Dev.Dev. Dev.Dev. Design #3 Design #2 Dev.Dev.Dev.Dev. ASIC / ASSP / 2 Chip AP SoC Extended Product life Platform Approach Enables Horizontal and Vertical Scalability

Copyright 2012 Xilinx Page 16 Zynq-7000 AP SoC Applications Mapping

© Copyright 2009 Xilinx Copyright 2012 Xilinx Device Table

Copyright 2012 Xilinx Page 18 Zynq-7000 Device Table Processing System

Copyright 2012 Xilinx Page 19 Zynq-7000 Device Table Programmable Logic and Packages