Upgrade developments in Clermont-Ferrand Romeo Bonnefoy and François Vazeille Tilecal upgrade meeting (CERN, 13 June 2014) ● Handling tools ● Deported HV system ● Front End readout 2 next talks: ● Neutron certification of active Dividers (François Vazeille) ● Status report of the FATALIC4 project (Laurent Royer) 1

Handling tools 2 ● Clermont-Ferrand tools operational Slider at 90° Basket Alignment on the Girder-Ring: on the free larger Ring Modifications can be made with respect to Barcelona services

3 ● Not compatible with the Barcelona developments ▪ Patch Panel and Service tools. ▪ No bearing screw on the Slider  Strength fully on the Girder Rings. Strongly screwed Clermont-Ferrand proposition (Several times explained) 3 ▪ Poor and damaging contact of the Slider Alignment and contact on the small Ring where glue and foam are located  No accuracy.  Damages of the foam. Responsibilities must be clarified.

● Implementation in the Building 175 HV Prague HV Crate DCS HV bus 4 Long HV cables 4 Short HV cables 4 Round Connectors 4 Electronics room Module area HV Crate HV Bus boards and HV cables Deported HV System Performances shown at the last Tilecal upgrade session

Present option for the tests 5

HV output #16 Prague HV Power Supply in Building 175 6

DCS monitoring in Building 175 7

●Procedure ▪ Connections ● Connect the HV Bus cards outside the Finger. ● HV Tesla: Output #16 in the rear part (Ready) ● Canbus: this one of the other Tesla modules (Ready). ● HV crate LPC: 4 HV outputs connected to 4 HV Blue Multiconductor cables. - Channels 1-12, 13-24, 25-36, Several options playing with four 20 m long cables (Labels 1 to 4) and one 100 m long cable (Label 100 m). - WARNING: put the “black connector loads” in the not used HV crate outputs. ▪ Working ● HV crate LPC: Switch on in the rear part (close to the Main). ● HV Tesla: select channel #16 on the front part. ● DCS Monitor: - Click on HV Module 4 (  Tile Slice Drawer #29). - Switch on and choose the individual HV values as usually with the DCS. Actions in Blue and Red. 8

Front End readout Main Board 2-3 Daughter Board All-in-1 ▪ “All-in-1 card “ - The options 2 (Clermont-Ferrand) and 3 (Argonne) have main functionalities in this very Front-End card, using a specific ASIC. - Today: Status report of the option 2 developed by Clermont-Ferrand. ▪ “Main Board 2-3” - Light version because main functions are in the “All-in-1 card”. - Today: Status report of the board suited to the two options and developed by Clermont-Fd. ● General framework 9

● “All-in-1 card” ▪ Version 1 made by Baptiste Joly. - Only one channel: FATALIC 3 (Current conveyor) TACTIC 1 (ADC) DAC (Calibration). - DAC  Chicago study (Ordered by 3 bits coming from DB and 2 LVDS commands to start the injection ranges). ▪ Version 2 : evolution of Version 1 suited to FATALIC4 (3 TACTIC 2 inside) - Main Board 2-3  LHC clock at 40 MHz. - FATALIC 4  2 gains (2x12bits) on 12 lines LVCMOS □ Always the Medium Gain □ High or Low Gain + 2 additional bits: Gain selection, Data synchronization. 10

● “Main Board 2-3” □ Architecture as close as possible to the Chicago developments (4 FPGA’s), but: no analog signals and no ADC’s. Besides, we take benefit from the Tilecal works with Stockholm DB. □ Data collection of 12 “All-in-1” (Clermont-Fd) or 12 “QIE” (Argonne) pin connector for each “All-in-1” 2 40-pin connectors for each “QIE”, with common and dedicated signals. □ Developed by Romeo Bonnefoy. □ Additional “Debug mode” for a readout without DB (USB 2 link at a low data flow). □ Role of the FPGA’s - To serialize the data. - To make the digital sums (Cs calibration). - To drive control signals. 11

1 single connector per channel Similar to Chicago: emulate same ADC Chicago signals Emulate ADC Chicago I2C signals Same SPI controls Same connector plus a second one (More control signals) 12

● Status and planning □ “All-in-1” Version 2 (With FATALIC4) - Mid-July: Final lay out, PCB routing, order of components. - End July: order of 14 PCB’s. - End August: reception of 14 PCB’s, order of cabling. - End September: reception of completed PCB’s. □ “All-in-1” Version 1 -Today status: scheme almost completed but for the choice of the 40-pin connector. - Before end-June: Final lay out, PCB routing, order of components. - End June: order of 2 PCB’s. - Mid-July: reception of PCB’s, cabling at home. 13

□ “Main Board 2-3” -Today status: ◦ Architecture fully defined 4 FPGA ’s Cyclone IV. ◦ Allocation of FPGA pins (with Quartus): OK. ◦ Scheme almost completed ◦ In progress the choice of some components (Example: connectors). ◦ In progress the VHDL code. - Before End June: Lay out completion and routing, order of some components. - End June : Order of one PCB. - July: Completion of VHDL code. - Mid-July: Reception of PCB and order of cabling. - End-August: Reception of completed PCB. 14

□ At home tests of “Main Board 2-3” and “All-in-1” - End-August: MB + “All-in-1” V1, with USB2 Debug. - End-September: MB + “All-in-1 ” V2, with USB2 Debug. - October: Performances of FATALIC4 chips through the MB. - November: Complete set MB + 12 “All-in-1” + Daughter Board + KC705 (or VC707) commercial cards + PC. □ CERN tests - December (Bldg175): MB + 12 “All-in-1” V2 + Daughter Board. - End 2014 or beginning 2015 (Bldg 175): MB + “QIE” (Argonne) : ◦ 4 additional Main Boards. ◦ 36 additional “All-in-1”. ◦ Full tests in Bldg 175 : 4 MB + 45 “all-in-1” + 4 Daughter Boards. ◦ Ready for Test Beam. 15 Other information from the next talk of Laurent Royer on the “Status report of the FATALIC4 project”

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