International ERD TWG Emerging Research Devices Working Group Face-to-Face Meeting Emerging Research Memory Devices Victor Zhirnov March 18, 2009

2 Hiro Akinaga Ralph Cavin Ahn Chen U-In Chung Mike Garner Zoran Krivokapic Muralidhar Ramachandran Ken Uchida Rainer Waser In-Seok Yeo Victor Zhirnov

3 Agenda u Review decisions from 2008 meetings u Content changes u Structure changes u Review revised memory table draft u Technical Discussion on Specific Emerging Memory Devices u Plans for

4 Summary of decided content changes u Drop Engineered Tunnel Barrier Memory from section v A natural evolution of FG memory u Add entry for NW phase-change memory  Add entry for Spin-torque transfer memory

Memory Table 5 Capacitance based Resistance-based Ferroelectric FET memory Nanomech anical Memory STTRAM Thermal Pase Change Electroche mical Memory Electronic Effects Memory Macromole cular Molecular Memories Memory Storage Mechanism Remnant polarization on a ferroelectric gate dielectric Electrostati cally- controlled mechanical switch Thermo- chemical Ion transport and Multiple mechanism s Not known redox process redox reaction Cell Elements 1T 1T1R or 1D1R Device Types FET with FE gate insulator 1) nanobridge / cantilever 1) Fuse/Antifuse Memory 1) cation migration 1) Charge trapping M-I-M (nc)-I-M Bi-stable switch 2) telescoping CNT 2) anion migration 2) Mott transition 3) Nanopartic le 2) nanowire PCM 3) FE barrier effects Korean ERD to provide input New classification

6 Summary of decided structure changes u Back to the single table format u Modified memory classification

A3, Classification of ER Resistance-based Memory Thermal Phase change memory: # PCRAM, >>> PIDS, Nanowired PRAM # Fuse / Antifuse memory, Pt/NiO/Pt, Electrochemical memory # cation migration, Cu:TCNQ? # anion migration, so-called ReRAM Electronic effect memory ex. Charge trapping ex. Mott transition (no experimental data) ex. Ferroelectric barrier effect AKINAGA, STRJ ERD Agreed WAS: Fuse/Antifuse memory WAS: Ionic memory

Memory Classification Discussion u In principle, the classification (thermal effect, electrochemical/ion migration effect, electronic effect) is okay. u In the more detailed list and in the text, we should make clear that there are quite a lot of intermixtures. For example, v the fuse/antifuse effect is considered as a thermochemical redox effect, which shows similarities with the anion- migration effect (which is also called valence change memory, VCM, effect). v Cu:TCNQ should be included, as suggested, as one (very specific) example of the cation migration effect. 8

Technical Discussion on Specific Emerging Memory Devices u Electronic Effects Memory/Charge Trapping u Nanomechanical memory 9

10 CNT cross-bar memory Expectations: n=10 12 bits/cm 2, f=100 GHz Rueckes T. et al., SCIENCE 289 (5476): JUL Moving Atoms u Each memory element is based on suspended crossed carbon nanotubes. u Cross-bar array of CNT forms mechanically bi-stable, electrostatically-switchable device elements at each cross point. u The memory state is read out as the junction resistance. Concept

11 Scaling Law in CNT Electromechanical Devices R. Lefèvre, 1 M. F. Goffman, 1 V. Derycke, 1 C. Miko, 2 L. Forró, 2 J. P. Bourgoin, 1 P. Hesto 3 Phys. Rev. Lett. 95, (2005) Young’s modulus Correction factor (1.21…1.45) L=700 nm, D=10 nm L=480 nm, D=10 nm L=700 nm, D=10 nm 500 nm H=230 nm =1.456 = Laboratoire d'Electronique Moléculaire, CEA-DSM SPEC, CEA Saclay, France 2 EPFL, CH-1015, Lausanne, Switzerland 3 Institut d'Electronique Fondamentale, CNRS, Université Paris 11, France

12 Calculation of pull-in voltages for carbon- nanotube-based nanoelectromechanical switch M. Dequesnes, S. V. Rotkin, and N. R. Aluru Nanotechnology 13 (2002)

13 Pull-in voltage increases with size scaling 10 nm 1 nm Dequesnes Lefèvre H=1 nm

14 Summary on nanomechanical memory u The projections for WRITE voltage and WRITE energy depend on the length of nano-electro-mechanical element u For very small length, the operating voltage might be too high for practical use, as follows from theoretical analysis

15 Electronic Effects Memory u Charge injection and trapping v Simmons and Verderber, “New conduction and reversible memory phenomena in thin insulating films”, Proc. Royal Soc. Lond. A 301 (1967) 77 AlSiOAu Resistance-change memory

16 Simmons-Verderber memory element u Unipolar/non-polar switching v Charging traps in insulator u ‘Forming process’ is critical v Strongly suggestive of positive ion (Au) injection into insulator 2 ns 100 ns WriteErase I

17 Energy Diagram, V=0

18 Energy Diagram, V>0 V<  0 (energy of localized levels) V>  0 (energy of localized levels)

19 Memory effect: Charge injection

20 Memory effect: Charge storing

‘Benchmark’ memory cell 21 Cell size, l<100 nm Store time, t s >10 8 s Write time, t w <10 -7 s Read time, t r <10 -7 s Read Voltage, V r ~1 V Read current, I r ~10 -6 A Read current density, J r >10 4 A/cm 2 Driver: Cell Scaling Driver: Array Scaling

22 What is the minimum barrier height for the charge-based NVM? Store EbEb Thermionic leakage current (ideal case): E bmin Min. barrier height for NVM High-barrier are needed for Non-volatile memory E b, eVMax. retention 0.74 ms ms ms 1.41 month years EbEb

Retention Analysis: Minimum Barrier Height 23 N=1 Free-electron gas Richardson’s equation Memory cell abstraction E bmin One-electron1.27 eV Many-electron1.45 eV

24 BB BB ff V s1 V s2 Vs0Vs0 V s2 >V s1 VrVr VbVb E Fme Limitations of Charge Trapping Electronic Effects Memory Store: E b > eV Read:  b =E b +  f I r =max  f =0

V r =1 Volt (  f =0 – to get highest J r ) 25 MaterialKm*m* r J r, A/cm 2 tsts SiOx E-08 s TiOx x E+13 s Both the read current and retention time do not meet the requirements of the benchmark memory element.

Triangle barrier abstraction 26 EbEb EbEb E b -V s VsVs

Rectangular barrier abstarction 27 a bb VsVs V r V 12 EFEF E Fme EcEc EtEt EcEc EtEt EcEc EcEc EtEt EtEt

I r =max: E c ~E t ~E F 28 a bb VsVs V r V 12 EFEF E Fme EtEt EtEt EtEt

Read voltage at read current ~1  A 29 Triangle barrier Rectangular barrier 12 V 21 V eV r ~7-8*E b eV r ~8-10*E b

Summary on Charge Trapping Electronic Effects Memory u A simple analysis is offered, which concludes that scaling of this technology below 100 nm might be difficult, as any conceivable material combination is very far away from being able to solve the “voltage-time dilemma” v Fast write and read times conflict with nonvolatility and logic voltage levels u Paper in preparation v Schroeder, Zhirnov, Cavin and Waser 30

2009 Activities v Fundamental study n Physical performance bounds for emerging memories  Team: Rainer Waser (Aachen U), Herbert Schroeder (Aachen U), Ralph Cavin (SRC), Victor Zhirnov (SRC) u 2009 Presentations (Zhirnov and Waser) v MRS Tutorial: Physics of Emerging Nonvolatile Memories v MRS Invited: Fundamental Limits and Trade-Offs for Flash Memory u SRC/NSF-ASTAR Forum on 2020 Semiconductor Memory Strategies: Processes, Devices, and Architectures v Date: October 27-28, 2009 v Place: Singapore-Fusionpolis 31

Plans for u Quantitative estimates of performance for the various types of memories v Work in progress – to be continued u Including ‘storage technologies’ in ERD  Continue discussing magnetic race-track memory u Develop a process for reviewing Memory Technology Entries 32