Supplementary notes for pipelining LW , SUB ,, BEQ ,, ; assume that, condition for branch is not satisfied OR ,,.

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Presentation transcript:

Supplementary notes for pipelining LW ____,____ SUB ____,____,____ BEQ ____,____,____ ; assume that, condition for branch is not satisfied OR ____,____,____ ADD____,____,____ Prepared by: Cem Ergün

IF/ID Clock Cycle 1 LWbefore REGISTERS READ REGISTER 1 / READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2 DATA MEMORY ADDRESS WRITE DATA READ DATA ALU ZERO RESULT ADD EX M WB RegWrite MemToReg CONTROL Branch MemRead MemWrite RegDst ALUOp ALUSrc MUX 0 1 ALU CONTROL Sign Extend MUX 0 1 I[15-11] I[20-16] I[15-0] M WB MUX 1 0 RegWrite MemToReg << 2 MemReadMemWrite Branch ID/EX EX/MEMMEM/WB INSTRUCTION MEMORY ADDRESSINSTRUCTION ADD PC 4 MUX 0 1 PCSrc

Clock Cycle 2 SUBLWbefore DATA MEMORY ADDRESS WRITE DATA READ DATA ALU ZERO RESULT ADD MUX 0 1 ALU CONTROL MUX 0 1 M WB MUX 1 0 MemToReg << 2 MemReadMemWrite Branch EX/MEMMEM/WB INSTRUCTION MEMORY ADDRESSINSTRUCTION ADD PC 4 MUX 0 1 REGISTERS READ REGISTER 1 / READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2 EX M WB RegWrite MemToReg CONTROL Branch MemRead MemWrite RegDst ALUOp ALUSrc Sign Extend I[15-11] I[20-16] I[15-0] RegWrite IF/ID ID/EX PCSrc

Clock Cycle 3 BEQSUBLWbefore DATA MEMORY ADDRESS WRITE DATA READ DATA WB MUX 1 0 MemToReg MemReadMemWrite Branch MEM/WB INSTRUCTION MEMORY ADDRESSINSTRUCTION ADD PC 4 MUX 0 1 REGISTERS READ REGISTER 1 / READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2 RegWrite MemToReg CONTROL Branch MemRead MemWrite RegDst ALUOp ALUSrc Sign Extend I[15-11] I[20-16] I[15-0] RegWrite IF/ID ALU ZERO RESULT ADD EX M WB MUX 0 1 ALU CONTROL MUX 0 1 M WB << 2 ID/EX EX/MEM ALUOp RegDst ALUSrc PCSrc

Clock Cycle 4 ORBEQSUBLWbefore MUX 1 0 MemToReg INSTRUCTION MEMORY ADDRESSINSTRUCTION ADD PC 4 MUX 0 1 REGISTERS READ REGISTER 1 / READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2 RegWrite MemToReg CONTROL Branch MemRead MemWrite RegDst ALUOp ALUSrc I[15-11] I[20-16] RegWrite IF/ID ALU ZERO RESULT ADD EX M WB MUX 0 1 ALU CONTROL MUX 0 1 << 2 ID/EX ALUOp RegDst ALUSrc Sign Extend I[15-0] I[5-0] DATA MEMORY ADDRESS WRITE DATA READ DATA M WB MemReadMemWrite Branch EX/MEM Zero PCSrc

Clock Cycle 5 ADDORBEQSUBLW MemToReg INSTRUCTION MEMORY ADDRESSINSTRUCTION ADD PC 4 MUX 0 1 ALU ZERO RESULT MUX 0 1 ALU CONTROL MUX 0 1 ALUOp RegDst ALUSrc I[5-0] DATA MEMORY ADDRESS WRITE DATA READ DATA M WB MemReadMemWrite Branch EX/MEM Zero PCSrc ADD << 2 MUX 1 0 REGISTERS READ REGISTER 1 / READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2 RegWrite MemToReg CONTROL Branch MemRead MemWrite RegDst ALUOp ALUSrc Sign Extend I[15-11] I[20-16] I[15-0] RegWrite IF/ID EX M WB ID/EX

Clock Cycle 6 after ADDORBEQSUB MemToReg INSTRUCTION MEMORY ADDRESSINSTRUCTION ADD PC 4 MUX 0 1 DATA MEMORY ADDRESS WRITE DATA READ DATA WB MemReadMemWrite Branch Zero PCSrc REGISTERS READ REGISTER 1 / READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2 RegWrite MemToReg CONTROL Branch MemRead MemWrite RegDst ALUOp ALUSrc Sign Extend I[15-11] I[20-16] I[15-0] RegWrite IF/ID MUX 1 0 ALU ZERO RESULT ADD EX M WB MUX 0 1 ALU CONTROL MUX 0 1 << 2 ID/EX ALUOp RegDst ALUSrc I[5-0] M WB EX/MEM

Clock Cycle 7 after ADDORBEQ MemToReg INSTRUCTION MEMORY ADDRESSINSTRUCTION ADD PC 4 MUX 0 1 DATA MEMORY ADDRESS WRITE DATA READ DATA WB MemReadMemWrite Branch Zero REGISTERS READ REGISTER 1 / READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2 RegWrite MemToReg CONTROL Branch MemRead MemWrite RegDst ALUOp ALUSrc Sign Extend I[15-11] I[20-16] I[15-0] RegWrite IF/ID MUX 1 0 ALU ZERO RESULT ADD EX M WB MUX 0 1 ALU CONTROL MUX 0 1 << 2 ID/EX ALUOp RegDst ALUSrc I[5-0] M WB EX/MEM

Clock Cycle 8 after ADDOR MemToReg INSTRUCTION MEMORY ADDRESSINSTRUCTION ADD PC 4 MUX 0 1 DATA MEMORY ADDRESS WRITE DATA READ DATA WB MemReadMemWrite Branch Zero RegWrite MemToReg CONTROL Branch MemRead MemWrite RegDst ALUOp ALUSrc Sign Extend I[15-11] I[20-16] I[15-0] RegWrite IF/ID MUX 1 0 ALU ZERO RESULT ADD EX M WB MUX 0 1 ALU CONTROL MUX 0 1 << 2 ID/EX ALUOp RegDst ALUSrc I[5-0] M WB EX/MEM MUX 1 0 REGISTERS READ REGISTER 1 / READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2

Clock Cycle 9 after ADD MemToReg INSTRUCTION MEMORY ADDRESSINSTRUCTION ADD PC 4 MUX 0 1 DATA MEMORY ADDRESS WRITE DATA READ DATA WB MemReadMemWrite Branch Zero RegWrite MemToReg CONTROL Branch MemRead MemWrite RegDst ALUOp ALUSrc Sign Extend I[15-11] I[20-16] I[15-0] RegWrite IF/ID MUX 1 0 ALU ZERO RESULT ADD EX M WB MUX 0 1 ALU CONTROL MUX 0 1 << 2 ID/EX ALUOp RegDst ALUSrc I[5-0] M WB EX/MEM MUX 1 0 REGISTERS READ REGISTER 1 / READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2