Robust Low Power VLSI Selecting the Right Conference for the BSN FIR Filter Paper Alicia Klinefelter November 13, 2011

Robust Low Power VLSI Motivation  FIR design competitive  Lowest in power and energy  No paper yet  Need to find conference  Should choose right venue for work  Multivariate optimization 2

Robust Low Power VLSI Outline  Appropriateness Criteria  FIR Design Characteristics  Conference Descriptions  CICC  ISLPED  VLSI  Comparison 3

Robust Low Power VLSI Conference Criteria 1.Conference Prestige Special Topics 3.Impact/Novelty 4.Probability of Acceptance 5.Deadline 6.Text Requirement 7.Figures 8.Location 4

Robust Low Power VLSI Design Characteristics  Programmable, Sub-threshold, and four-channel FIR Filter  Lowest in power and energy 5 This Work[1][2][3] Design Type30-tap, 8-bit FIR8-tap 8x8 FIR14-tap 8x8 FIR8-tap, 8-bit FIR Number of Channels4111 Technology0.13μm Supply Voltage0.4V0.32V0.36V0.6V Operating Frequency200kHz23MHz187MHz24kHz Power Dissipation219nW56uW5.9mW87uW

Robust Low Power VLSI Design Characteristics  Pros  Flexibility/Programmability  Low power, sub-threshold  Synthesizeable  Cons  Circuit-level techniques  Available figures 1.ED Curves 2.Architecture 3.Frequency Response a)15, 30, 60 taps 4.Filtered Data 5.Comparison Table 6.Die Photo and Operation Summary 6

Robust Low Power VLSI CICC  IEEE Custom Integrated Circuits Conference  Relevant Topics  Location: San Jose, CA  Deadline: April 7, 2012  Conference: September 9 th – 12 th  Text: 4 pages 7 1.Analog Circuit Design 2.Systems on Chip and 3D 3.Memory 4.Biomedical, Actuators, MEMS, and Sensors 5.IC Manufacturing 6.Power Management 7.Simulation and Modeling 8.Test, Debug, and Reliability 9.Wired Communications 10.Wireless Designs

Robust Low Power VLSI ISLPED  International Symposium on Low Power Electronics and Design  Relevant Topics  Location: Redondo Beach, CA  Deadline: March 9, 2012  Conference: July 30 th – Aug. 1 st  Text: 6 pages 8 1. Architecture, Circuits, and Technology 1.1. Technologies and Digital Circuits 1.2. Logic and Microarchitecture Design 1.3. Analog, MEMS, Mixed Signal and Imaging Electronics

Robust Low Power VLSI VLSI Symposium  VLSI Technology/Circuit Symposium  Relevant Topics  Location: Honolulu, HI  Deadline: January 23, 2012  Conference: June 12 th – 15 th  Text and Figures: 2 pages 9 1.RF and wireless communication 2.Wireline transceiver and I/O design 3.Digital circuit techniques for processor, memory, and complex SOC architectures and implementations 4.Clock generation and distribution 5.Analog and mixed signal 6.…

Robust Low Power VLSI Location 10 VLSI Honolulu, HI 4800 mi CICC San Jose, CA 2400 mi ISLPED Redondo Beach, CA 2200 mi

Robust Low Power VLSI Comparison VLSICICCISLPED Prestige Factor123 Topics?AvailableNot ReallyAvailable Design ImpactMid-HighHighMid-High Probability Accept321 DeadlineJanuary 23, 2012April 7, 2012March 9, 2012 Text~1 page~3 pages~5 pages Figures~1 page Location123 11

Robust Low Power VLSI Conclusions  VLSI  Prestigious, competitive  Topic available  Paper is best so far  Appropriate for length  Less Appropriate for figures  Few circuit-level techniques  Great location 12

Robust Low Power VLSI References  [1] Myeong-Eun Hwang; Raychowdhury, A.; Keejong Kim; Roy, K.;, "A 85mV 40nW Process-Tolerant Subthreshold 8x8 FIR Filter in 130nm Technology," VLSI Circuits, 2007 IEEE Symposium on, vol., no., pp , June  [2] Wei-Hsiang Ma; Kao, J.C.; Sathe, V.S.; Papaefthymiou, M.C.;, "187 MHz Subthreshold-Supply Charge-Recovery FIR," Solid-State Circuits, IEEE Journal of, vol.45, no.4, pp , April  [3] Yu-Ting Kuo; Tay-Jyi Lin; Yueh-Tai Li; Chih-Wei Liu;, "Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.57, no.7, pp , July

Robust Low Power VLSI Questions? 14