SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM SE-IR Corporation 87 Santa Felicia Dr. Goleta, CA (805)

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM General System Architecture DSP frame grabber FPA or CCD CamIRa head Pattern generator PC

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Camera Head architecture BIAS cards Voltage References high speed A/D cards Clock driver cards Linear power supplies BACKPLANE LVDS IN CLOCKS LVDS IN CONTROLS LVDS OUT VIDEO Analog pixel offset or trigger card

SE-IR Corporation 11/04 Goleta, CA (805) T ypical A/D channel Architecture Buffer stage optional current source offset stage Prog. gain stage A/D Control logic Buffer stage Buffer stage input programmable Offset voltage Gain Select (4 programmable) Voltage Reference digital output to backplane High, medium, low gain select 14 bit 10 and 20 MSPS 16 bit 2 MSPS 1, 2 and 4 channels cards available

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Clock drivers Architecture Clock input to clock channel output selection matrix clock channel 1 clock channel 4 slew rate control (each channel) clock rails (each channel)

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Clock drivers Settable high/low clock rails for each ch. –Settable rail voltage range: +/-10V –Min. rail to rail voltage:.25V –Max rail to rail voltage: 20V Slew rate is adjustable for each channel –max. slew rate : 1 nsec/V –min. slew rate : 20 nsec/V

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Analog pixel offset Buffer stages Address counters offset summing stage analog output buffer Trigger/Sync inputs 10 bit 100MHz DAC 512Kx16 SRAM global offset 8 bit digital output port High, medium, low range select Offset Control logic Control logic Reference voltage Digital control bus Offset clocks

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Bias supplies Architecture bias supply 1 bias supply 5 bias supply 4 bias supply 2 voltage reference buffer block selectable output block selectable output

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Bias supplies Adjustable bias supply voltage: +/- 10V Max. current: 125mA per bias supply Selectable inline resistors for current measurement Common high precision voltage reference for all bias supplies Buffered outputs for channel to channel isolation

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Voltage References Architecture high prescision 10V reference 12 bit QUAD OFFSET VOLTAGE DACs for A/Ds A/D references Bias references CONTROL LOGIC 4 pos gain select 4 channels Current source references

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM DSP architeciture camera head control opt. Proc. coef. list NUC Gi*(Xi+Bi) + Ci coef. lists dual memory buffers pixel reorder list download and frame capture memory USB 2.0 interface 16 bit digital video LVDS/TTL parallel output LVDS/CMOS/TTL in LVDS out

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM DSP Single PCI slot card format, USB2.0 control up to 80 MHz pixel rate 16 bit inputs and outputs Scalable bit arithmetic 16 bit normalized result Coef. lists are 2M pixels long (4M opt.) Arbitary pixel re-ordering allows mirror, rotation and bad pixel replacement

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM DSP cont’d 16 bit frame capture memory synchronous downloads of memory lists Optional processing or display module Data stream used dedicated pipeline ( PC bus is not used for data stream)

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Pattern Generator architecture Integration control 4 ch Pattern Memory 512k x 32 Operand memory Instruction decoder Pattern memory address counter Jmp reg 1 Jmp reg 2 Counter 1 Counter 2 Counter 3 USB 2.0 interface LVDS drivers A/D delays 4 ch Clock Synthesizer.02-80MHz Instruction memory Instruction address counter Ext. status (4 ch)

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Pattern Generator Single AT slot card.01 to 80MHz clock synthesizer 26 clock lines –18 general purpose clocks –4 A/D conversion clocks (programmable delay) –4 integration clocks (programmable duty cycle) 512K subpattern memory

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Pattern Generator cont’d Clock patterns defined as subpatterns Subpattern sequencing controlled by program instructions Memory usage: –Typical clock program for 640x480 FPA pattern words executable instructions

SE-IR Corporation 11/04 Goleta, CA (805) CamIRa TM Pattern generator cont’d Controllable polarity on all clocks Programmable integration clocks without reloading timing patterns A/D clock delays programmable –2 nsec to 512 nsec in 2 nsec increments External status lines for synchronization to external event