Adam Meyer, Michael Beck, Christopher Koch, and Patrick Gerber

 LGA 1155 Socket  DMI ◦ 5 GT/s  32 nm manufacturing process  3.4 GHz system clock

 Memory Controller ◦ Inside package  Increases performance  L1 ◦ Contained in the core  L2(mid level cache MLC) ◦ Intermediate  L3 ◦ Shared between all cores

Intel Smart Cache: Demo

 L1 Cache ◦ 64 KB (32 data, 32 instruction) ◦ Has 4 of these caches, one for each core  L2 Cache ◦ 256 KB ◦ Has 4 of these caches, one for each core  L3 Cache ◦ 8 MB ◦ Shared

 L1 ◦ 4 cycles  L2 ◦ 11 cycles  L3 ◦ 25 cycles  RAM ◦ Approx. 107 cycles

 Integrated Memory Controller (IMC) ◦ Reduces latency  Hyperthreading (HT) ◦ Allows one core to appear as two

 Static RAM ◦ Data available until power loss ◦ Idle: 97.5 Watts ◦ Running: Watts

 Word Size ◦ 64 Bits  Floating Bit Register ◦ 80 Bits  Vector Register ◦ 128 Bits

 Address Bus ◦ 32 Bits ◦ 32 GB Max  Instruction Set ◦ SSE 4.1/4.2 AVX instruction set ◦ 64 Bits  Data Bus ◦ 64 Bits

 Price/Performance ◦ $ (with heatsink and fan)  Speed ◦ 5 GT/s ◦ 3.4 GHz  Cache Sizes

 CPU World. (2012). Intel Core i7-2600K. Retrieved April 8, 2012, from CPU World: K%20CM html  Gasior, G. (2012). Exploring the impact of memory speed on Core i7 performance. Retrieved April 8, 2012, from The Tech Report:  Intel. (2012). Intel Smart Cache: Demo. Retrieved April 8, 2012, from Intel.com: technology/intel-smart-cache.html  PC Perspective. (2012). Sandy Bridge-E Processor Review. Retrieved April 8, 2012, from PC Perspective: Sandy-Bridge-E-Processor-Review/Power-Consumption-and-Perform  Vertrees, R., Coelho, R. O., & Torres, G. (2012). All Core i7 Models. Retrieved April 8, 2012, from Hardware Secrets: