CMPE 421 Advanced Computer Architecture Supplementary material for Pipelining PART1

2

PM Midnight Time Pipelining Lessons: Laundry Machine example Slow Way If each load is done sequentially it takes 6 hours

4  Pipelined laundry takes 3.5 hours Pipelining Lessons: Laundry Machine example Quick way 6 PM 789 Time

5 Single Cycle Datapath

6 ALU Pipeline Divisions Divide datapath into steps 1 cycle each Instructions range from 3-5 stages in MIPS pipeline RegsRegs RegsRegs Data Memory Instr. Memory IF Instruction Fetch ID/RF Register Fetch EX Execution MEM. Memory WB Write back PCPC

7 Revised: Single Cycle Datapath

8 Multicycle Datapath/Control xtend 3216 Instruction [25–21] Instruction [20–16] Instruction [15–0] Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrit e IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op [5–0] Instruction [31-26] Instruction [5–0] M u x 0 2 Jump address [31-0] Instruction [25–0] 2628 Shift left 2 PC [31-28] 1 1 M u x M u x 0 1 ALUOut Memory MemData Write data Address write control

9 Pipeline Datapath

10 Load Datapath: Stage 1 A

11 Load Datapath: Stage 2 B

12 Load Datapath: Stage 3

13 Load Datapath: Stage 4 A

14 Load Datapath: Stage 5 B

15 Store Datapath: Stage 3

16 Store Datapath: Stage 4

17 Store Datapath: Stage 5

18 Corrected Pipelined datapath for lw