May 17, USB2.0 Host Controller John S. Howard Staff Engineer Intel Architecture Labs Intel Corporation

May 17, Agenda w Project Overview w Key Features Overview – USB 2.0 Host Controller Architecture – High-Speed Host Controller  Interface Architecture  Interface Data Structure Overview/Benefits – Power Management w Host Controller Compliance Program w Summary

May 17, Project Overview w Enhanced Host Controller Specification for USB – Defines the register (hardware/software) interface for a USB 2.0 capable host controller w Revision 0.95 will be the first public release – License agreement provides reciprocal royalty free license to manufacture compliant discrete USB 2.0 host controllers based on this specification

May 17, Project Overview w Revision 1.0 is the final specification – License agreement provides reciprocal royalty free license to manufacture compliant USB 2.0 host controllers based on this specification w Intel developed specification with contributions so far from – NEC, Lucent, Philips, Compaq and Microsoft – Licensees can also contribute to specification Continued

May 17, Project Overview w Specification Development methodology – Developed in parallel with USB 2.0 core specification – Low-risk approach  Leverage existing USB 1.1 HC implementations and knowledge base – Provide solutions to well-known USB host controller problems – Focus on reasonable hardware/software complexity tradeoffs – Validate features whenever possible  Built prototype driver and host controller in parallel with specification w Host Controller Compliance Program – Ensures host controllers are compliant to the specification

May 17, USB 2.0 Host Controller Architecture w Multi-function Controller delivers 3 port speeds – Simplifies High-speed Host Controller  Optimize for high-speed functionality – Reuses USB 1.1 Host Controller Designs (drop-in) – Allows port availability independent of presence of high-speed capable software USB 2.0 Host Controller (HC) Port 1 Companion USB HCs for FS/LS Port 1 Port 2 Port Owner Control(s) Port 1 Port 2 Port Routing Logic Port N HC Control Logic/Data Buffering Enhanced HC Control Logic Enhanced Data Buffering Port 2 Port N High-Speed (Enhanced Interface) USB HC

May 17, USB 2.0 Host Controller Architecture: Port Routing Rules w Ports owned by Companion controllers when HS HC software is absent w When HS HC Software is present, it “configures” High-Speed HC then: – Retains ownership for high-speed devices – Releases individual port ownership if attached device is not high speed  Routing Logic signals a disconnect on HS HC and a connect on Companion HC – Ownership returns to HS HC on a disconnect event Companion USB 1.1 HC X Port Register High Speed HC TransceiverTransceiver Port Routing Logic Port Owner Control HC Configured Port Register

May 17, High-Speed Host Controller Interface Architecture w Three-part Interface – PCI Space – Register Space – Shared Memory Work Interface w PCI Configuration Registers – PCI Class Codes – Memory space base address for register space – Power Management Interface PCI Class Code, etc. USB Base Address PCI Power Management Interface PCI Configuration Register

May 17, High-Speed Host Controller Interface Architecture w Memory-based I/O Registers – Capability Registers  Implementation-specific, read-only parameters for driver – Operational Registers  Host controller management  List Management  Port control registers Capability Registers Operational Registers Memory-Based I/O Registers

May 17, High-Speed Host Controller Interface Architecture w Shared Memory Work Lists – Two schedule Lists (periodic, asynchronous) – Queuing data structures  Used for transfer types guarantee delivery – Different data structures used for isochronous  Different data structures for high- and full-speed  Optimized for streaming isochronous data  No support for retries Shared Memory Work Lists Periodic List Asynchronous List

May 17, High-Speed Host Controller Interface Architecture (Overview) Capability Registers Operational Registers Memory-Based I/O Registers PCI Class Code, etc. USB Base Address PCI Power Management Interface PCI Configuration Register Shared Memory Work Lists Periodic List Asynchronous List

May 17, Shared Memory Work Lists Queuing Data Structure w Queues are used for ALL Non-Isochronous transfers w 1 queue per endpoint w Each queue element (transaction descriptor) describes a buffer – I.e. 1 to many transactions – Up to 20 Kbytes per transaction descriptor  16Kbytes with worst-case buffer alignment w No Hardware/software sync required to add work to a queue w Architecture optimized to provide efficient memory accesses – Block, burst accesses – Reduced average number of memory accesses to start transaction

May 17, Shared Memory Work Lists Queuing Data Structure (Ex.) Transfer Descriptors Linked to queue head by software driver Transfer Descriptors Linked to queue head by software driver qTD 0 qTD 2 Data Buffer 0 Data Buffer 1 qTD 1 Data Buffer 2 Queue Head: Static queue head information Dynamic transfer execution area Queue Head: Static queue head information Dynamic transfer execution area SetupSetup StatusStatus Setup Data Receive Data Buffer DataData Example: Control Transfer Initial Condition: QHD empty Example: Control Transfer Initial Condition: QHD empty Example: Control Transfer Software attaches list to QHD Example: Control Transfer Software attaches list to QHD Current (A) (A) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Setup Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD for 1 transaction Next (B)(B) (B) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Data Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD until done (B) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Data Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD until done CurrentCurrent CurrentCurrent NextNext (C) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Status Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD for 1 transaction (C) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Status Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD for 1 transaction (C)(C)

May 17, Shared Memory Work Lists Isochronous Data Structures w Used only in periodic list – Time-oriented data structure – “Frame number” encoded in topology of list  Position of work item in periodic list determines when it will be “seen” and executed by the host controller – No hardware (micro)-frame arithmetic required w Different data structures for high-speed and low-speed – High-speed data structure optimized for large transfers – Full-speed data structure optimized for split-transaction support

May 17, Shared Memory Work Lists Hardware Scatter/Gather w All transfer data structures are scatter/gather capable w Simple hardware implementation – No pointer arithmetic required – Simple concatenation of page pointer to page offset to generate buffer address – Software initializes page offset, hardware manages page pointers and page offset based on transfer progress

May 17, Power Management w High-speed controller power management – USB port power management – PCI Bus Power Management Interface w Provides per/port capabilities for managing bus power as defined in USB specification w Support defined for PCI Advanced Power management interface – Compliant with PCI Bus Power Management Interface Specification, Revision 1.1

May 17, USB 2.0 Host Controller Compliance Program w Compliance testing includes – Standard USB 2.0 Compliance tests – Standard USB 2.0 Electrical tests – Host controller-specific Interface Functional Testing w Availability – HC compliance test will be available from Intel  Method of distribution (to be defined) – Alpha-level tools available in Q – Beta-level tools available in Q – Production release available with release of 1.0 host controller specification

May 17, USB 2.0 Host Controller Compliance Program w HC-specific compliance software under development at Intel w Special compliance devices (high-speed and full/low speed) w Special-purpose application and driver for controlled testing and analysis w Interface Functional Testing – Device Interoperability – USB 2.0 protocol and transfer extensions – System Interaction – Etcetera, … HC Compliance Application HC Compliance Test Driver EHCI Unit Under Test USB 2.0 Hub (s) HS Compliance Device(s) FS/LS Compliance Device (s)

May 17, Summary w Low-risk Introduction – All ports are HS/FS/LS Capable – Legacy (non-high-speed aware) software just works – Re-use of 1.1 controllers simplifies high-speed controller w Interface optimized for good memory accesses efficiency w Reasonable tradeoff of hardware/software complexity

May 17, Summary w PCI power management compliant w Host controller compliance program w Revision 0.95 for discrete HC Q – Gating item is validation of 2 discrete host controllers w Revision 1.0 in 2001 – Gating item is validation of integrated host controller Continued