FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Topics n Basics of sequential machines. n Sequential machine specification. n Sequential machine design processes.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Sequential machines n Use registers to make primary output values depend on state + primary inputs. n Varieties: –Mealy—outputs function of present state, inputs; –Moore—outputs depend only on state.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR FSM structure

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Constraints on structure n No combinational cycles. n All components must have bounded delay.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Synchronous design n Controlled by clock(s). –State changes at time determined by the clock. –Inputs to registers settle in time for state change. –Primary inputs settle in time for combinational delay through logic. n Machine state is determined solely by registers. –Don’t have to worry about timing constraints, events outside the registers.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Non-functional requirements and optimization n Performance: –Clock period is determined by combinational logic delay. n Area: –Combinational logic size usually dominates area. n Energy/power: –Often dominated by combinational logic. –May be improved by latching values.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Models of state machines n Register-transfer: –Combinational equations for inputs to registers. n State transition graph/table: –Next-state, output functions described piecewise.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR State transition graph n Each transition describes part of the next- state, output functions: S1 S2 S3 0/010 1/1-0

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Register-transfer structure n Registers fed by combinational logic: Combinational logic DQDQDQDQDQDQ

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Block diagram n Purely structural description: B1 A B2

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Symbolic values n A sequential machine description may use symbolic, not binary values. –Symbolic values must be encoded during implementation. n Encoding may optimize implementation characteristics: –Area. –Performance. –Energy.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR STG vs. register-transfer n Each representation is easier for some types of machines. n Example: counter.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Counter state transition graph n Cyclic structure: 0 1/1 1 1/2 6 1/7 7 1/0 …

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Counter register-transfer function n Specify using addition: –Next_count = count + 1. n Regular structure of logic.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Example: 01 string recognizer n Recognize 01 sequence in input string: recognizer

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Recognizer state transition graph Bit 1Bit 2 0/0 1/1 1/0 0/0

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Mealy vs. Moore machine n Moore machine: –Output a function of state. n Mealy machine: –Output a function of primary inputs + state.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Sequential machine definition n Machine computes next state N, primary outputs O from current state S, primary inputs I. n Next-state function: –N =  (I,S). n Output function (Mealy): –O = (I,S).

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Reachability n State is reachable if there is a path from given state. n May be created by state encoding: s0s1 s2s3

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Homing sequence n Sequence of inputs that drives the machine to a given state. s0s1 s2

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Equivalent states n States are equivalent if they cannot be distinguished by any input sequence: s1s2 s3s4 0/0 -/0 -/1 -/0 1/0

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Networks of FSMs n Functions can be built up from interconnected FSMs: M1M2 x y I1 O1 I2 O2 External connections Internal connections

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Illegal composition of Mealy machines Combinational logic DQ Combinational logic DQ

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Communicating FSM states s1 s2 M1 0/0 1/0 -/1 s3 s4 M2 0/0 -/0 1/1

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Product machine n Two connected machines: RS i1o1 i2 o2

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Component STGs

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Behavior of connected machines RS i1o1 i2 o2 R1S1001 R2S2010 R3S1000 R3S1000

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Forming product machine n Form Cartestian product of states: –R1S1, R1S2, R2S1, R2S2, R3S1, R3S2. n For each product state, determine the combined behavior of each product transition: –Required inputs. –Produced output. –Next product state.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR State assignment n Find a binary code for symbolic values in machine. –Optimize area, performance. –May be done on inputs, outputs as well.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Optimizing state assignments n Codes affect the next-state, output logic. –Compute conditions based on state. n Best code depends on the input, output logic and its interaction with state computations.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Encoding a shift register n Symbolic state transition table for shift register: 0S S100 0S01S001 1S01S101 0 S010 1S10S110 0 S011 1S11 1

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Bad encoding n Let S00 = 00, S01 = 01, S10 = 10, S11 = 10. n Logic: –Output = S1 S0’ + S1’ S0 –N1 = I –N0 = I S1’ + I S1

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Good encoding n Let S00 = 00, S01 = 01, S10 = 10, S11 = 11. n Logic: –Output = S0 –N1 = I –N0 = S1

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR One-hot code n N-state machine has n-bit encoding. n Ith bit is 1 if machine is in state i. n Comparison: –Easy to tell what state the machine is in. –Easy to get the machine into an illegal state (0000, 1111, etc.). –Uses a lot of registers.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR Common factors in state coding n Consider this set of transitions: –0, s1 OR s2 -> s3, 1 n Want to choose a code that easily produces s1 OR s2. –S1 = 00, S2 = 01.

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR State codes in n-space 0 s1 code = 111 s2 code =

FPGA-Based System Design: Chapter 5 Copyright  2004 Prentice Hall PTR State codes and delay