2017 IFIP/IEEE International VLSI-SOC Conference Proposal

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Presentation transcript:

2017 IFIP/IEEE International VLSI-SOC Conference Proposal Boston, Massachusetts USA Martin Margala

Location Benefits Attractive Location – Choice between Urban and Resort location Traditionally, from mid-September to mid October very mild weather Major Travel Hub for International Travel More than 100 semiconductor companies have Massachusetts as their main East Coast US location 20 major Universities (many among the best in the world) in New England with significant VLSI related programs (more than 40 if we include NY, NJ and PA) Full support of IEEE Boston

Realistic Goals Increase # of submitted papers by 40% Increase selectivity Increase the # of full registrations by 20% Increase industrial participation and sponsorship New attractive student programs – industrial tours, student competitions

Facilities and Transportation Several possible hotel and conference facilities are possible within the vicinity (25 miles) of the City of Boston, from urban to coastline (Waltham, Woburn, Cambridge, Charlestown, Lowell, Salem,…) Easy access using local rail and bus transportation

Potential Sponsors EDA Companies: Cadence, Mentor Graphics CPU/GPU Companies: Intel, AMD, NVIDIA SOC Companies: Broadcom, Qualcomm, Cisco, Oracle Mixed-Signal: Analog Devices, Maxim, Fairchild, Infineon, NXP, RFMD Test Companies: Teradyne Defense Companies: Raytheon, Lockheed- Martin, BAE

Team Conference Chair - Martin Margala, UML Program Chair and Co-Chair - TBA Panel Chair - TBA Special Sessions Chair - TBA Finance Chair – Robert Alongi, IEEE Boston Publication Chair - TBA Publicity Chair - Ayse K. Coskun, BU Sponsorship Chair - TBA Local Arrangement – Robert Alongi, IEEE Boston Web Manager - TBA

Budget - Income Registration Sponsorship $15,000 Regular ($500) x 170 attendees = $85,000 Student ($250) x 75 attendees = $18,750 Sponsorship $15,000 Total $118,750

Looking Forward to Seeing You In Boston, Massachusetts Thank you