ECE 331 – Digital System Design Transistor Technologies, and Realizing Logic Gates using CMOS Circuits (Lecture #23)

ECE Digital System Design2 Transistor Technologies Two transistor technologies: 1. Transistor-Transistor Logic (TTL) 2. Metal Oxide Semiconductor (MOS)

ECE Digital System Design3 TTL Technology TTL = Transistor-transistor Logic Dominant technology prior to the emergence of CMOS technology. Not as suitable for large-scale integration as CMOS technology. Largely obsolete for new designs.  Good for labs and educational use because it is more robust than CMOS.

ECE Digital System Design4 TTL Technology Bipolar Junction Transistor (BJT)  Base – controls current flow in transistor  Collector – current flow enters transistor  Emitter – current flow exits transistor npn BJT  Collector, Emitter: n-type semiconductor  Base: p-type semiconductor pnp BJT  Collector, Emitter: p-type semiconductor  Base: n-type semiconductor

ECE Digital System Design5 MOS Technology CMOS  Complementary Metal Oxide Semiconductor NMOS  N-channel MOSFET PMOS  P-channel MOSFET MOSFET  Metal Oxide Semiconductor Field Effect Transistor

ECE Digital System Design6 DrainSource x = "low"x = "high" (a) A simple switch controlled by the inputx V D V S (b) NMOS transistor Gate (c) Simplified symbol for an NMOS transistor V G Substrate (Body) NMOS Transistor

ECE Digital System Design7 NMOS Transistor Four-terminal device  Simplified three-terminal representation Conducting channel is N-type material Drain pulled high (connected to supply voltage) in digital circuits Source pulled low (connected to ground) in digital circuits

ECE Digital System Design8 NMOS Transistor Gate-to-Source Voltage (V GS )  Controls the drain current (i D ) via an electric field Oxide (silicon dioxide) insulates the gate from the drain and the source  i G ~= 0 Amps  i D ~= i S  Low power

ECE Digital System Design9 NMOS Transistor Operates as a binary switch in digital circuits V G = 0V(V S = GND = 0V)  V GS ~= 0V  “looks like” an open switch (in the cutoff region; “off”) I D = I S = 0A V G = VDD(V S = GND = 0V)  V GS ~= VDD  “looks like” a closed switch (in the saturated region; “on”)

ECE Digital System Design10 Gate x = "high"x = "low" (a) A switch with the opposite behavior of the NMOS transistor V G V D V S (b) PMOS transistor (c) Simplified symbol for a PMOS transistor V DD DrainSource Substrate (Body) PMOS Transistor

ECE Digital System Design11 PMOS Transistor Four-terminal device  Three-terminal simplified representation Conducting channel is P-type material Drain pulled low (connected to ground) in digital circuits Source pulled high (connected to supply voltage) in digital circuits

ECE Digital System Design12 PMOS Transistor Gate-to-Source Voltage (V GS )  Controls the drain current (i D ) via an electric field Oxide (silicon dioxide) insulates the gate from the drain and the source  i G ~= 0 Amps  i D ~= i S  Low power

ECE Digital System Design13 PMOS Transistor Operates as an binary switch in digital circuits V G = 0V(V S = VDD = Supply Voltage)  V GS ~= -VDD(V SG ~= VDD)  “looks like” an closed switch (in the saturated region; “on”) V G = VDD(V S = VDD = Supply Voltage)  V GS ~= 0V(V SG = 0V)  “looks like” a open switch (in the cutoff region; “off”) I D = I S = 0A

ECE Digital System Design14 (a) NMOS transistor V G V D V S = 0 V V S =V DD V D V G Closed switch whenV G =V DD V D = 0 V Open switch whenV G = 0 V V D Open switch whenV G =V DD V D V Closed switch whenV G = 0 V V D =V DD V (b) PMOS transistor NMOS and PMOS Transistors

ECE Digital System Design15 NMOS transistors PMOS transistors CMOS Logic Circuit

ECE Digital System Design16 Voltage Levels in CMOS Circuits Voltages are used to represent Logic values in CMOS (and TTL) circuits: Logic 1 = VDD Logic 0 = GND

ECE Digital System Design17 Voltage Ranges in CMOS Circuits

ECE Digital System Design18 CMOS Logic Beneficial to use NMOS and PMOS in same design  No steady state drain (or gate) current  Low power dissipation Configuration of NMOS and PMOS transistors  For Output of CMOS circuit = Logic 0 PDN (NMOS transistors)ON PUN (PMOS transistors)OFF  For Output of CMOS circuit = Logic 1 PDN (NMOS transistors)OFF PUN (PMOS transistors)ON

ECE Digital System Design19 (a) Circuit V f V DD V x (b) Truth table and transistor states T 1 T 2 on off on fx T 1 T 2 CMOS Circuit: Inverter (NOT)

ECE Digital System Design20 CMOS Circuit: NAND Gate

ECE Digital System Design21 CMOS Circuit: NOR Gate

ECE Digital System Design22 CMOS Circuit: AND Gate NAND Gate Inverter

ECE Digital System Design23 CMOS Circuit: OR Gate

ECE Digital System Design24 CMOS Circuits Analysis

ECE Digital System Design25 The functional behavior of a CMOS circuit can be determined by analyzing the behavior of the individual PMOS and NMOS transistors, and, thus, the behavior of the PUN and PDN. CMOS Circuits: Analysis

ECE Digital System Design26 CMOS Circuits: Analysis (Steps) Determine the state of each transistor for each input combination. Determine the output of the CMOS circuit for each input combination. Derive the corresponding Truth Table Determine the Boolean Expression that defines the behavior of the CMOS circuit.

ECE Digital System Design27 Example #1: Analyze the following CMOS circuit to determine the logic function that it implements. CMOS Circuits: Analysis

ECE Digital System Design28 CMOS Circuit: Analysis (Ex. #1)

ECE Digital System Design29 Example #2: Analyze the following CMOS circuit to determine the logic function that it implements. CMOS Circuits: Analysis

ECE Digital System Design30 CMOS Circuit: Analysis (Ex. #2)