NET+OS 6.1 Training

BSP

NET+OS 6.1 BSP Initialization Memory map New features Debugging Porting Issues

Overall view of the BSP Identify and process Reset types: –hardware reset, –power-up reset, –software reset, –software restart, –wakeup reset from sleep mode Perform Memory test. Load LED and Simple Serial driver for debugging before the kernel and other device drivers are loaded. Set C library startup from GreenHills and GNU. Load the device drivers; Ethernet, DMA, PCI, I2C, USB, LCD).

BSP Source Code Initialization code is in NETOS\src\bsp\arm9init directory. Platform code is in NETOS\src\bsp\platforms\ns9750_a. Common code is in NETOS\src\bsp\common (shared with different platforms). Device drivers are in NETOS\src\bsp\devices directory. Bootloader code is in NETOS\src\bsp\bootloader directory. Profiler code is in NETOS\src\bsp\profiler directory. Include files are in NETOS\h\arm9, NETOS\src\bsp\h, NETOS\h, and NETOS\src\bsp\platforms\ns9750_a directories. Register definitions are in NETOS\h\arm9 directory. Configurable parameters are defined in netos\src\ \bsp\platforms\ns9750_a \bsp.h.

Linker Script Directives Linker scripts determine memory layout image.ldr, rom.ldr (GNU) image.lx rom.lx (GHS) customize.lx and customize.ldr (in platforms directory), adjust values for your application Sections added for ttb table and non-cache region NON_CACHE_MALLOC_SIZE

Building the BSP Build from netos/src/bsp directory In GNU platform specified in command line to make file –make PLATFORM=platform –In GNU Warnings are now treated as errors and stricter warning checking is enabled (-Wall) In GHS platform open netCentral.bld, select standard_bsp.bld

Reminder to …. Modify defines in bsp.h to enable drivers We now have four serial ports, two are UART and one is SPI and one is not connected. The boards default to support USB host Only big endian is supported There is no EEPROM support for NVRAM

Initialization and Start up Hardware initialization Software initialization Memory map Device driver initialization Exception and interrupt handler setup Interfacing with higher level modules: RTOS, TCP/IP, ACE, and Application Code

Initialization Flow Start Reset.s Init.s ncc_init.c main() tx_kernel_enter tx_application_ define netosStartup root.c [applicationStart()] Your application code

Hardware Initialization Reset_Handler: First routine to be executed Identify and process reset types (hardware reset, power-up reset, software reset, software restart, and wakeup reset from sleep mode). Initializes SDRAM on CS4 using the values from settings.s (RAS/CAS) USB configuration and Bbus rest Calls nccInit using a small stack on CS4 Jumps to C library Reset_Handler.doc

Initialization: nccInit Check to see if we are in the debugger or if a software restart occurred. Call setupSimpleSerial Call customizeSetupGPIO Call customizeReadPowerOnButtons Call customizeMemoryTest Programs chip selects (Base and Mask)

Initialization: (cont) nccInit: Check to see if the application will fit into RAM (linker directives) ncc_init.doc

Memory Map Address RangeSizeSystem Functions 0x – 0x0FFF FFFF256 MBSystem Memory Chip Select 4 Dynamic Memory 0x – 0x1FFF FFFF256 MBSystem Memory Chip Select 5 Dynamic Memory 0x – 0x2FFF FFFF256 MBSystem Memory Chip Select 6 Dynamic Memory 0x – 0x3FFF FFFF256 MBSystem Memory Chip Select 7 Dynamic Memory 0x – 0x4FFF FFFF256 MBSystem Memory Chip Select 0 Static Memory 0x – 0x5FFF FFFF256 MBSystem Memory Chip Select 1 Static Memory 0x – 0x6FFF FFFF256 MBSystem Memory Chip Select 2 Static Memory 0x – 0x7FFF FFFF256 MBSystem Memory Chip Select 3 Static Memory

Memory map continued 0x – 0x8FFF FFFF256 MBPCI Memory 0x – 0x9FFF FFFF256 MBB-Bus Memory 0xA – 0xA00F FFFF1 MBPCI IO 0xA – 0xA01F FFFF1 MBPCI CONFIG_ADDR 0xA – 0xA02F FFFF1 MBPCI CONFIG_DATA 0xA – 0xA03F FFFF1 MBPCI Arbiter 0xA – 0xA04F FFFF1 MBBBUS-to-AHB Bridge 0xA – 0xA05F FFFF1 MBJBIG 0xA – 0xA06F FFFF1 MBEthernet Communication Module 0xA – 0xA07F FFFF1 MBMemory Controller 0xA – 0xA08F FFFF1 MBLCD Controller 0xA – 0xA09F FFFF1 MBSystem Control Module 0xA0A – 0xFFFF FFFF1526 MBReserved

SDRAM Memory settings Settings.s contains the memory controller register settings for SDRAM. (not in debugger) If you use different memory parts you must modify this file (PC133). RAS and CAS Delay Registers Dynamic memory configuration registers

SRAM (flash) Table defined in bsp.c defines the register settings for SRAM parts SRAM memory configuration registers, specifies 16 bit or 32-bit. Static memory Read Delay registers

Initialization : Main() execute POST SetupVector Table Enable MMU (data cache) DDI First Level Initialization Start threadX main.doc

Initialization: Loading RTOS Set up FIQ and IRQ stack. Create threadx (system) timer thread (stack size 1024, priority is 0). Call BSP routine to set up system timer clock and timer 2 and to create root thread (stack size and priority are configurable in appconf.h file) and start it. Start RTOS scheduler. threadx_init.doc

Root Thread: netosStartup() Load device drivers Read parameters from NVRAM and configure dialog. Call netosstartTCP() to initialize and start TCP/IP stack and ACE. Set up real time source and install time zone. Start up application. root_thread.doc