Advanced Computers and Communications (ACC) Faculty Advisors: Dr. Charles Liu Dr. Helen Boussalis 10/25/20121NASA Grant URC NCC NNX08BA44A Student Assistants: Airs Lin Aleksander Milshteyn Gabriel Nunez Evan Tsai

Handshaking Protocol 7/19/2012NASA Grant URC NCC NNX08BA44A2

Handshaking Protocol 7/19/2012NASA Grant URC NCC NNX08BA44A3 Flow of data: PC (Application)  USB Output  FPGA Input PC (Application)  USB Input  FPGA Output Begin End

Simple Parallel I/O Processor writes data into output port Processor reads data from input port No latching of data No indication that data has changed

Strobe Synchronization Strobe – additional control signal accompanies the data Notifies the microcontroller when new data is ready at the input port Notifies external devices when new data is ready at an output port A latch asserts interrupt The microcontroller must read data before next input strobe occurs Problem: Data can be sent by input device without receiver being ready

Handshaking Synchronization A second control line is used Form of acknowledgement or busy signal Solves the problem of data being sent before the receiving end is ready Potential race condition exist: Microcontroller is testing its Busy bit, prior to the Output Device asserting busy. It forces Microcontroller to send another chunk of data to Output Device, since the busy signal has not reached it on time. Race Condition!

Full Handshaking (Solving Race Condition) Uses both edges of the strobe and busy signals The Request for Data signal is held high when it is ready to accept new data from Input Device The Data Available signal is held high when Input Device is ready to send new data Based on two above conditions – Data Transfer occurs and Busy is asserted When the data recipient (Microcontroller) acknowledges receipt of data, the Request signal is lowered Input Device “learns” that data has been received, removes the data, and waits for the next data request

EZ-USB Basic Block Diagram

Modes In ‘Ports’ mode, all the IO pins are general-purpose IO ports. ‘GPIF master’ mode uses the PORTB and PORTD pins as a 16-bit data interface to the four EZ-USB endpoint FIFOs EP2, EP4, EP6 and EP8. In this ‘master’ mode, the EZ-USB FIFOs are controlled by the internal GPIF, a programmable waveform generator that responds to FIFO status flags, drives timing signals using its CTL outputs, and waits for external conditions to be true on its RDY inputs. In the ‘Slave FIFO’ mode, external logic or an external processor interfaces directly to the EZ-USB endpoint FIFOs. In this mode, the GPIF is not active, since external logic has direct FIFO control. Therefore, the basic FIFO signals (flags, selectors, strobes) are brought out on EZ-USB pins. The external master can be asynchronous or synchronous, and it may supply its own independent clock to the EZ-USB interface.

Custom Handshaking Interface (Ports Mode) 7/19/2012NASA Grant URC NCC NNX08BA44A11

WriteToFPGA Mode 7/19/2012NASA Grant URC NCC NNX08BA44A12

ReadFromFPGA Mode 7/19/2012NASA Grant URC NCC NNX08BA44A13

Windows Application 7/19/2012NASA Grant URC NCC NNX08BA44A14

Loop Test 7/19/2012NASA Grant URC NCC NNX08BA44A15

Handshaking Block-Diagram FPGA Side 7/19/2012NASA Grant URC NCC NNX08BA44A16

Handshaking WR Mode (Encoding) 7/19/2012NASA Grant URC NCC NNX08BA44A17

Handshaking WR Mode (Encoding) 7/19/2012NASA Grant URC NCC NNX08BA44A18

Handshaking RD Mode (Encoding) 7/19/2012NASA Grant URC NCC NNX08BA44A19

Handshaking RD Mode (Encoding) 7/19/2012NASA Grant URC NCC NNX08BA44A20

7/19/2012NASA Grant URC NCC NNX08BA44A Handshaking Protocol - Project Steps (2013) Compiling and Debugging of Cypress FX2 Board & Encoding/Decoding Application