L i a b l eh kC o m p u t i n gL a b o r a t o r y Trace-Based Post-Silicon Validation for VLSI Circuits Xiao Liu Department of Computer Science and Engineering.

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Presentation transcript:

l i a b l eh kC o m p u t i n gL a b o r a t o r y Trace-Based Post-Silicon Validation for VLSI Circuits Xiao Liu Department of Computer Science and Engineering The Chinese University of Hong Kong

Silicon Debug: Bottleneck in Prototype-to- Volume Time Pre-silicon verification cannot ensure the design correctness Smaller design margins – increasing chance of performance failures Un-modeled defects – higher tester escapes Higher design complexity – more time and vectors to validate Acknowledgment: Yu-Chin Hsu, Furshing (Kevin) Tsai, Wells Jong, Ying- Tsai Chang, Novas Test/DebugDesign Silicon Prototype ConceptVolume 7 to 8 months Decreasing 6 to 7 months Increasing! Data Quest (2002, 2004) report

Post-Silicon Validation Problem Post-silicon validation is expensive One respin: millions of $ Economic impact of delayed ramp to production: tens of millions $ Post-silicon validation is challenging Very limited observability Scan is not enough Industry silicon spins or above 0% 10% 20% 30% 40% 50% ASSPASIC source: Numetrics Management Systems, Inc.

Trace-Based Post-Silicon Validation Pro Observe the system’s behavior in real-time Exercise functionality and timing not verified pre-silicon Detect problem difficult to reproduce on tester Con Low coverage Hardware overhead Debug Configuration Data Analysis, Diagnosis Design-for-Debug Insertion Data dump Acknowledgment: Yu-Chin Hsu, Furshing (Kevin) Tsai, Wells Jong, Ying- Tsai Chang, Novas How to conduct signal tracing effectively with low-cost hardware?

Trace-Based Post-Silicon Validation Infrastructure [DATE-09, ATS-10, DATE-11] [ATS-08, DAC-09]

Tracing Solutions for Debugging Design Error Design errors violate the pre-defined specification Signal selection for visibility enhancement [DATE-09] Challenge: Logic values are not known during signal selection Solution: Traced signal AXXXXX BXXXXX C0110X DXXXXX EXXXXX A11XXX B00XXX C0110X DX1001 EX10XX Visibility estimation metricTrace signal selection Guide Our solution achieves higher visibility

Tracing Solutions for Debugging Design Error Design errors violate the pre-defined specification Multiplexed tracing [DATE-11] Trigger point Trace buffer size Current solution: “static” tracing Time Trigger point Trace buffer size Time Proposed solution: “multiplexed” tracing Trace those FFs with propagated evidences facilitates to detect this error Our solution provides higher design error detection capability

Tracing Solution for Debugging Electrical Error Electrical errors lead to reduced frequency of the circuits Sensitive to electrical environment Coupling noise, Power supply noise, Driving strength, … Extremely difficult to eliminate during pre-silicon verification and manufacturing test Challenge: Difficult to localize in post-silicon validation Solution: in-situ tracing Selectively trace signals that monitors potential errors on speedpaths Our solution can detect error At its root-cause site On error occurrence cycle Without “golden vectors”

Low-Cost Trace Data Transfer Fabric Design Challenge: High flexibility v.s. Low cost Solution: Interconnection fabric design [DAC-09] Signal classification Design optimization Challenge: High Bandwidth v.s. Low cost Solution: Reusing test access mechanism [ATS-08] Challenge: Systematical tracing v.s. Low cost Solution: Flexible interconnection fabric design Non-correlated signals Correlated signals Our solution minimizes hardware cost Our solution reduces routing cost Our solution enables systematical tracing

Thank you for your attention !

Backup Slides Trace signal selection for visibility enhancement   Multiplexed tracing for detecting design error   Interconnection fabric design   Signal tracing for debugging electrical error  

Experimental Results of Signal Selection for Visibility Enhancement 

Experimental Results of Multiplexed Tracing 

DfD Cost Comparison of s38417 

Speedpath-Related Electrical Errors Model Trace those FFs that make the above node values visible facilitates to detect this error Required visible node values: a_in2(0), b_in1(0), c_out(0) 

Detection Quality Evaluation: Signal Selection for Non-Zero Visibility CircuitTotal Signal # Relevant Signal # Selected Signal # Detected Pro. Event # Occurred Pro. Event # Detection Quality Time (s) s %45.5 s %125.3 DMA %150.3 usb %77.4 des %668.3 