JOP Design Flow Microcode make JopSim ModelSim Java Quartus JVM

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Presentation transcript:

JOP Design Flow Microcode make JopSim ModelSim Java Quartus JVM Eclipse make Java JVM VHDL FPGA IO bus Wishbone ACEX Spartan Cyclone

The Project 4/5 programming languages 267 directories, 1403 files VHDL, Java, Microcode, C, (Verilog) 267 directories, 1403 files 68k LOC find . –name *.vhd – print | xargs wc Java: 30565 VHDL: 23080 Microcode (.asm): 10089 C: 4141 4 FPGA types, 6 target boards AK: JVMHW JOP Design Flow

Don‘t Panic This complexity is not unusual There is a master Makefile Linux kernel: 6M LOC! There is a master Makefile A single target can be built Calls batch files Help Some documentation is available (pdf and web) e-mail to Schoeberl Yahoo! Groups : java-processor AK: JVMHW JOP Design Flow

Directories vhdl asm java The hardware description of JOP The JVM in microcode java System sources (JVM, JDK) Target applications Tools AK: JVMHW JOP Design Flow

Directories cont. quartus xilinx Project files for Altera FPGA boards Each board and variation in its own directory xilinx Project files for Xilinx FPGA boards AK: JVMHW JOP Design Flow

File Types Source Generated Configuration .asm, .vhd, .java JVM assembly: .vhd, .mif, .dat Quartus: .sof, … JOPizer: .jop Configuration Project: Makefile, .bat Quartus: .qsf, .cdf AK: JVMHW JOP Design Flow

JOP JVM Microcode jvm.asm System JVM.java System Startup.java Jopa core.vhd JVM Application Hello.java Memory files rom.vhd,… javac Synthesize Quartus classes.zip FPGA config. jop.sof JOPizer Hello.jop Configure Download

JOP Startup FPGA configuration Java application ByteBlaster download cable USB Flash on power up Watchdog -> PLD configures FPGA Java application Serial line Flash AK: JVMHW JOP Design Flow

Startup Configuration FPGA configuration PLD (MAX7064) ByteBlaster: cyc_conf_init.pof Flash: cyc_conf.pof Java application JVM (jvm.asm) on startup Loads the application (.jop) Defines download type Constants: FLASH, USB, SIMULATION AK: JVMHW JOP Design Flow

Targets Top level defines FPGA type IO top level defines board type jopcyc.vhd jopcyc12.vhd jopacx.vhd … IO top level defines board type scio_min.vhd scio_baseio.vhd scio_dspio.vhd AK: JVMHW JOP Design Flow

JVM + Library JVM Library Microcode (jvm.asm) Java (JVM.java, Startup.java, GC.java) Library JOP specific: util, ejip, joprt JDK: System, String,… AK: JVMHW JOP Design Flow

Native Functions Bridge between Java and the HW Special bytecode Memory, IO access Register, stack cache Special bytecode Implemented in microcode Translated in JOPizer Define in: jvm.asm com.jopdesign.sys.Native.java com.jopdesign.tools.JopInstr.java AK: JVMHW JOP Design Flow

Simulation VHDL with ModelSim High level with JopSim Board simulation HW related changes Testbench reads the memory content High level with JopSim System debugging (e.g. GC) Reads .jop files A JVM in Java Board simulation AK: JVMHW JOP Design Flow

Summary Modules Build JOP – VHDL files JVM – Microcode + Java Application – Java Build Jopa, Quartus -> FPGA configuration file (.sof) javac, JOPizer -> Java application file (.jop) Makefile + Batchfiles AK: JVMHW JOP Design Flow

More Information An Introduction to the Design Flow for JOP AK: JVMHW JOP Design Flow