Harris Corner Detector on FPGA Rohit Banerjee Jared Choi : Parallel Computer Architecture and Programming

Introduction to the problem

Corner detection Corner Detection Corners provide a lot of information Spending time to detect corners can significant reduce computation time * Image matching * Motion tracking * Robot Navigation

Application Specific Need Pixel Stream Output CORNER DETECTOR Want to be able to process images in real time. Corner detection is very memory intensive. CPU cannot process data fast enough because it had to store data to DRAM first.

Exploit arbitrary hardware parallelism to process more within the given time window

Harris Detector Basic Idea

Hardware Implementation

Processing Pipeline

Grayscale

Processing Pipeline

Sobel Filter

2D convolution

Convolution Buffer

After a while……

Convolution Buffer This column is ready to be processed 0 1 N-2 N-1

Convolution Buffer 0 1 N-2 N-1

Convolution Buffer 0 1 N-2 N-1

Processing Pipeline

Gaussian Filter

Processing Pipeline

Harris Response Harris Input ∑Gadxdx ∑Gadydy∑Gadxdy = Sxx Sxy Syy

Harris Response

Results PlatformExecution Time/ms Naïve Serial Implementation OpenCV18.12 SystemVerilog(50MHz)1.31

Results Platform Speedup of FPGA Implementation Naïve Serial Implementation OpenCV13.83

Results Hardware Approx. Power Consumption/W Intel i Cyclone IVE FPGA6.30

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