makefiles

makefiles Problem: You are working on one part of a large programming project (e. g., MS Word).  It consists of hundreds of individual.c files all linked together to form winword.exe.  You make a change to one of these.c files and now need to rebuild word.exe.  How do you do it without having to recompile hundreds of.c files that haven’t changed?

w/out makefiles g++ -o word.exe f1.c f2.c f3.c f4.c … f999.c But only f4.c has changed and only needs to be recompiled! Compiler option to create intermediate (object modules) files: g++ -c f1.c g++ -c f2.c … g++ -c f999.c g++ -o word.exe f1.o f2.o f3.o … f999.o Then I just manually do: g++ -c f4.c and then relink.

But how can I automatically determine only what needs to be recompiled?  Write a program that looks at the modification time of the.c file and the.o (or.exe) file. If the mod time of the.c file is more recent than the mod time of the.o (or.exe) file, then we know that we know that we need to recompile and relink.  But I don’t want to write this program! (Someone already built this into the Java compiler, and MS Visual Studio.)

makefiles Consist of: 1.Comments (begin with #) 2.Definitions 3.Dependencies 4.Commands

makefiles Consist of: 1.Comments (begin with #) 2.Definitions 3.Dependencies 4.Commands  Comments: # # this is a comment. #

makefiles Consist of: 1.Comments (begin with #) 2.Definitions 3.Dependencies 4.Commands  Definitions (are like constants): CC = g++ -g or CC = g++ -O3 …  to use these definitions, evaluate with $(CC)

3. Dependencies a: b c d …  This means that a is dependent upon (needs) b and c and d …  What is word.exe dependent upon (below)?  g++ -o word.exe f1.o f2.o f3.o … f999.o  word.exe is dependent upon f1.o, f2.o, …, f999.o word.exe: f1.o f2.o … f999.o  What is f1.o dependent upon?

Dependencies & 4. Commands  Usually, a dependency is followed by a command to rebuild/recreate/update the entity to the left of the colon (called a tag).  Dependencies are hierarchical (i.e., top-down). word.exe: f1.o f2.o … f999.o g++ -o word.exe f1.o f2.o … f999.o g++ -o word.exe f1.o f2.o … f999.o f1.o: f1.c g++ -c f1.c g++ -c f1.c f2.o: f2.c g++ -c f2.c g++ -c f2.c…

makefile syntax target1 target2 target3 : prerequisite1 prerequisite2 <tab>command1<tab>command2<tab>command3 1. One or more targets (to the left of the colon). 2. Zero or more prereqs (after the colon). 3. Zero or more commands (each must be preceeded by a tab).

“Standard phony” targets  all Perform all tasks to build the application  install Create an installation of the application from the compiled binaries  clean Delete the binary files generated from sources  distclean Delete all the generated files that were not in the original source distribution  TAGS Create a tags table for use by editors  info Create GNU info files from their Texinfo sources  check Run any tests associated with this application  docsCreate (doxygen) documentation. (gjg)

Example (including definitions and comments) #for debug version: CC = g++ -g #for production version: #CC = g++ -O3 word.exe: f1.o f2.o … f999.o $(CC) -o word.exe f1.o f2.o … f999.o $(CC) -o word.exe f1.o f2.o … f999.o f1.o: f1.c $(CC) -c f1.c $(CC) -c f1.c…

Example (more than 1 command) #for debug version: CC = g++ -g word.exe:f1.o f2.o … f999.o echo link word.exe $(CC) -o word.exe f1.o f2.o … f999.o f1.o:f1.c echo compile f1.c $(CC) -c f1.c …

Example (make more than one) #for debug version: CC = g++ -g all:word.exe fred.exe … word.exe:f1.o f2.o … f999.o echo link word.exe $(CC) -o word.exe f1.o f2.o … f999.o f1.o:f1.c echo compile f1.c $(CC) -c f1.c …

Example make commands  make  Checks the first dependency that appears in the file makefile.  make all  Checks the all dependency in makefile.  make word.exe  make f1.o  make fred.exe  make –f myMakeFile all  Checks the all dependency in file myMakeFile.