Ivan Perić University of Heidelberg, Germany High-Voltage Pixel Detectors in Commercial CMOS Technologies for ATLAS, CLIC and Mu3e Experiments Ivan Perić University of Heidelberg, Germany

Overview Introduction: The High-Voltage CMOS Sensors and CCPDs Summary of the older results New applications: High-Voltage CMOS Detector for Mu3e experiment at PSI High-Voltage CMOS Detectors for ATLAS/CLIC at CERN TEM

High-voltage CMOS pixel detectors

HV CMOS detectors We start with a low voltage process: PMOS and NMOS transistors are placed inside their shallow wells. PMOS NMOS Shallow n-well Shallow p-well

HV CMOS detectors A deep n-well surrounds the electronics of every pixel. PMOS NMOS deep n-well

HV CMOS detectors The deep n-wells isolate the pixel electronics from the p-type substrate. PMOS NMOS deep n-well p-substrate

HV CMOS detectors Since the pixel-transistors do not “see” the substrate potential, the substrate can be biased low without damaging the transistors. In this way the depletion zones in the volume around the n-wells are formed. => Potential minima for electrons Charge collection occurs by drift PMOS NMOS deep n-well Drift Potential energy (e-) Depletion zone p-substrate

HV CMOS detectors Maximizing of the depleted regions improves performances (less capacitance and noise, more signal) – the best results can be achieved in high-voltage technologies. Example AMS 350nm HVCMOS: Typical reverse bias voltage is 60 V and the depleted region depth ~15 m. 20cm substrate resistance -> acceptor density ~ 1015 cm-3 PMOS NMOS deep n-well Drift Potential energy (e-) ~15µm Depletion zone p-substrate

HV CMOS detectors Maximizing of the depleted regions improves performances (less capacitance and noise, more signal) – the best results can be achieved in high-voltage technologies. Example AMS 350nm HVCMOS: Typical reverse bias voltage is 60 V and the depleted region depth ~15 m. 20cm substrate resistance -> acceptor density ~ 1015 cm-3 „Smart diode“ PMOS NMOS deep n-well Drift Potential energy (e-) ~15µm Depletion zone p-substrate

Capacitively Coupled Pixel Detectors CCPDs

Standard hybrid detector Pixel Readout chip Min. pitch ~50 μm Bumps Charge signal is transmitted Fully-depleted sensor Signal charge

CCPD with a “passive” sensor Pixel Readout chip Min. pitch < 50 μm Voltage signal is transmitted Requires bias resistors on the sensor… that can be implemented as punch-through structure Signal ~30mV for 250µm thick sensor (Cdet = 100fF) Fully-depleted sensor Signal charge

Active CCPD Pixel Readout chip Sensor implemented as HVCMOS Advantage: Charge to voltage amplification on the sensor chip Typical voltage signal ~100mV Easier capacitive transmission Can be thinned without signal loss Smart diode- or fully-depleted sensor Signal charge Signal >30mV for very thin sensors

Project results

„Proof of principle“ phase Project history 2006 „Proof of principle“ phase 350nm AMS HV technology Simple (4T) integrating pixels with pulsed reset and rolling shutter RO (Possible applications: ILC, transmission electron microscopy, etc.) 2) Pixels with complex CMOS-based pixel electronics (Possible applications: CLIC, LHC, CBM, etc.) 3) Capacitive coupled hybrid detectors based on a pixel sensor implemented as a smart diode array

Project history Efficiency vs. the in-pixel position of the fitted hit. Efficiency at TB: ~98% (probably due to a rolling shutter effect) Seed pixel SNR 27, seed signal 1200e, cluster 2000e The type 1 chip HVPixelM: Simple (4T) integrating pixels with pulsed reset and rolling shutter RO 21x21 µm pixel size Spatial resolution 3-3.8µm

Project history Signals and noise of a CAPSENSE pixel after 1015neq/cm2 Detection efficiency vs. amplitude Detection of signals above 330e possible with >99% efficiency. CAPPIX/CAPSENSE edgeless CCPD 50x50 µm pixel size

„Proof of principle“ phase New projects 4) 65nm UMC LV technology 2006 „Proof of principle“ phase 180nm AMS HV technology 350nm AMS HV technology Applications: 1) Mu3e experiment at PSI Monolithic CMOS pixels with CSA 2) ATLAS (and CLIC) Capacitive coupled pixel detectors based on smart sensors 3) Transmission electron microscopy integrating pixels with pulsed reset and rolling shutter RO – in-pixel CDS

Sensor concepts Pixel electronics is based on a charge-sensitive amplifier and optionally a comparator. The pixel signal/address is sent as an analog information. The signal processed by the digital circuits are on the chip periphery or on a separate chip. 1) Mu3e: The pixel signal is processed on the sensor chip itself -> monolithic pixel detector. 2) ATLAS: intelligent sensor concept. The pixel address is transmitted to an existing readout chip, like FEI4 or an strip-readout chip. Readout Electronics Readout Electronics Pixels

High-voltage CMOS detectors for Mu3e experiment Collaborating institutes: DPNC Geneva University PSI Particle Physics ETH Zürich Physics Institute Zürich University Heidelberg University: Physics Institute, KIP, ZITI

Mu3e experiment Mu3e experiment at PSI (Proposal: A. Schöning et. al.) Search for decay µ+ -> e+ e- e+ (4 orders of magnitude better than previous searches) This lepton flavor violating decay would be a sign for the theories beyond the Standard Model Background from other muon decays that generate electron and photons -> 3 electrons and 2 neutrinos Challenges: Low electron energy < 53 MeV High decay rate – 109 µ/s Good timing resolution Good momentum resolution – 0.5 MeV/c2 (1T) Good vertex resolution – 100µm Little material – 10-3 x0/layer e+ µ+ e+ ? γ* e- W+ e- e+ µ+ νµ νe e+ The decay is enhanced (BR 10-16) if one of the following theories apply: Grand unified models Left-right symmetric models Extended Higgs sector Large extra dimensions Branching ratio < 10-12 (SINDRUM) Standard model: The decay could be the result of the neutrino mixing Branching ratio < 10-50 unobservable

Mu3e detector Proposed: four layers of pixels ~ 80x80m2 size – HV CMOS monolithic detectors Time stamping with < 100ns resolution required to reduce the number of tracks in an image. Sensors should be thinned to ~50 m Triggerless readout Power ~ 200mW/cm2 cooling with helium Total area: 1.9 m2 275 M pixels 100 wafers (if 100% yield) B=1T Recurl pixel layers Outer pixel layers 3744cm2 7488cm2 Scintillator tiles 360cm2 µ+ Inner pixel layers Al target Scintillating fibres

Mu3e detector Proposed: four layers of pixels ~ 80x80m2 size – HV CMOS monolithic detectors Time stamping with < 100ns resolution required to reduce the number of tracks in an image. Sensors should be thinned to ~50 m Triggerless readout Power ~ 200mW/cm2 cooling with helium Total area: 1.9 m2 275 M pixels 100 wafers (if 100% yield) B=1T Recurl pixel layers Outer pixel layers Scintillator tiles Inner pixel layers Scintillating fibres

Mu3e detector Thinned chips Kapton PCB & Supporting structure The sensors of the size 1 x several cm (2 x several cm outer layers) will be glued onto a self supporting kapton structure and flexible PCBs Multi-reticle modules are planned. We do not need electrical connections between the reticles The guard rings at the reticle-edges should not lead to insensitivities. The charge is collected from substrate to nearest pixels. Thinned chips 2cm Pixels – active region Kapton PCB & Supporting structure 1cm ~0.5 mm EoC logic

Mu3e detector Thinned chips Kapton PCB & Supporting structure The sensors of the size 1 x several cm (2 x several cm outer layers) will be glued onto a self supporting kapton structure and flexible PCBs Multi-reticle modules are planned. We do not need electrical connections between the reticles The guard rings at the reticle-edges should not lead to insensitivities. The charge is collected from substrate to nearest pixels. Thinned chips 2cm Pixels – active region Kapton PCB & Supporting structure 1cm ~0.5 mm EoC logic

Readout concept for Mu3e The sensor pixels contain CMOS electronics based on charge sensitive amplifiers. The amplifier output signals are transferred to the readout cells on the chip periphery. The readout cells perform comparison with threshold, they store a time stamp when a hit is detected and they send the data according to the defined priority. A prototype with the full readout electronics have been submitted in August 2012. The electronics include: Pixels Readout cells

Sensor pixel 80 µm Amplifier LP R 80 µm A

Readout cell BL HitIn (CR filter) Comparator n In TS Memory Wr D Address S S x x Th Rd Priority 4-bit DAC R R In<0:3> En HitOut Read TS TSout RAMout RW

Mu3e test-chip in 180nm technology 1.8mm 42x36 pixels 30m Analog pixels 0.7m 2 metal layers Analog pixel layout Digital channels Pixel detector chip with a small matrix have been submitted in November 2011 and successfully tested. Pixel size 39x30 micrometers. Separated digital and analog block. Signal time measurements possible.

Signal and noise measurements The signal has been measured using various radioactive and x-ray sources. The capacitive test injection circuit has been used to measure noise and threshold dispersion. Thresholds can be tuned using in-pixel DACs.

Response speed measurements The digital part accepts only the comparator signals that are within the trigger window. Time resolution tests possible. Time resolution is the sum of time walk and signal collection time. Test signal Test signal Ampl. out Ampl. out Comp out Comp out Window del1 Window del2

Time walk measurement In-time efficiency vs. signal amplitude (40ns time window). Detection of signals > 1230 e with 40ns time resolution possible. Power consumption of the pixel 7.5 µW. We expect at least 1500 e from MIPs.

Collection time measurement Comparison of the response delay to capacitive test pulse (delay only caused by the amplifier) and the delay to IR pulse (delay caused by the amplifier and collection time). To assure that the amplifier delays are equal, we keep the signal amplitudes for both injections the same. The amplitudes are measured as ToT. ToT is proportional to the input charge. It does not depend on the amplifier rise times. Test signal Ampl. out Absorption of 850nm light ~14µm Similar spatial distribution of the charge generation as for MIPs 1400e Comp out N-well 5µ m 60% drift del2 10µ m IR laser signal Depleted (drift) Ampl. out 40% diffusion 1400e Comp out

Collection time measurement Charge collection time – IR laser, comparison with the fast capacitive injection. No measurable delay time difference.

High-voltage CMOS detectors for ATLAS Collaborating Institutes (preliminary list): CERN CCPM Marseille LBNL Berkeley University of Bonn University of Heidelberg

CCPD for ATLAS pixel detector We use one of the existing RO chips for the readout of an intelligent HVCMOS sensor. This approach simplifies the design of sensor and allows us to use the existing readout- and data-acquisition-systems. Intelligence: the pixels are able to distinguish a signal from the background and to respond to a particle hit by generating an address information. We replace the standard bump-bonded sensor with… Pixel readout chip (FE-chip) Pixel electronics based on CSA Bump-bond pad Bump-bond Pixel length = 250 μm Pixel sensor

CCPD for ATLAS pixel detector The HV CMOS sensor pixels are smaller than the standard ATLAS pixels, in our case 33μm x 125μm - so that three such pixels cover the area of the original pixel. The HV pixels contain low-power (~ 7μW) CMOS electronics based on a charge sensitive amplifier and a comparator. …the capacitive coupled HV CMOS sensor Pixel readout chip (FE-chip) Pixel electronics based on CSA Coupling capacitance Bump-bond pad Glue Transmitting plate Summing line 33x 125 μm Pixel CMOS sensor

CCPD for ATLAS pixel detector The electronics responds to a particle hit by generating a pulse. The signals of a few pixels are summed, converted to voltage and transmitted to the charge sensitive amplifier in the corresponding channel of the FE chip using AC coupling. The FEI4 and HVCMOS sensor are glued onto each other without bump bonding. Each of the pixels that couple to one FE receiver has its unique signal amplitude, so that the pixel can be identified by examining the amplitude information generated in FE chip. In this way, spatial resolution in - and z-direction can be improved. Pixel readout chip (FE-chip) Pixel electronics based on CSA Coupling capacitance Bump-bond pad Glue Transmitting plate Summing line 33x 125 μm Pixel CMOS sensor

Advantages compared to existing detectors No need for bump-bond connection between the sensor and readout chip – lower price, better mechanical stability, less material. Commercial technology – lower price. No need for bias voltages higher than 60V. Operation at temperatures above 0C is according to tests possible (irradiations to 1015 neq/cm2). Increased spatial resolution (e.g. 25m x 125m binary resolution) with the existing FE chip Smaller clusters at high incidence angles. Possibility of sensor-thinning without signal loss. Since we do not use bumps and FE chips can be thinned as well, the amount of material would be very low. Interesting choice for other experiments where low-mass detectors are needed such as CLIC, ILC, CBM, etc...

HV2FEI4 Pixel matrix: 60x24 pixels (readout by 20 x 12 FEI4 pixels) Pixel size 33 m x 125 m. IO pads for strip operation Pixel matrix 4.4mm Strip pads IO pads for CCPD operation

Signal transmitted capacitively CCPD operation FEI4 Pixels Signal transmitted capacitively CCPD Pixels 2 2 Bias A 3 3 Bias B 1 1 Bias C

Pixel electronics Amplifier CCPD electrode G SFOut Resistance Filter BL NMOS Comparator V-I convertor A (CR filter) D D Th Cap. Injection In<0:3> G G Select RW 4-bit DAC CCPD bus Programmable current Strip bus

6 pixels – layout Tune DAC Comparator Amplifier 33 µm

Measurement setup

Measurements with active pixels FEI4 HVCMOS Injection Test pad

Measurements with 22Na beta source

Conclusion The HVCMOS technology has first planned applications: Search for Mu->3e decay at PSI. 1.9m2 , 50 µm thin monolithic pixel sensor is planned, about 270M of 80x80 µm pixels. Readout is based on time stamps, time resolution 100ns. A test-chip with simplified readout and small pixels has been tested (measured time resolution < 40ns, noise 40 e). Test beam measurement done – first results soon. A larger prototype with full readout electronic have been submitted in August 2012. Engineering run is planned after the evaluation of the prototype. LHC experiments ATLAS. The concept: Intelligent sensors in HVCMOS technology readout by the existing readout ASCIs – capacitive coupled hybrid detectors. First module with a HVCMOS chip glued onto a FEI4 ROC works, the noise still high due to non-optimal setup. Test beam is planned. First measurements with a strip readout chips will be done soon. Irradiation ongoing. Measurements with HVCMOS chip glued onto TimePix soon. If the results are fine, we will submit a larger sensor within an engineering run. Another application for HVCMOS (SDA) detectors: TEM.

Implementation of “smart diodes” in 65nm technology - 2.5 µm pixels

Pixel detector in 65nm technology The first “smart diode” (SDA)-detector implemented in a low-voltage (UMC 65nm) CMOS technology. The pixel size is only 2.5 x 2.5 micrometers. We measure a very low noise - an effect of the small diode capacitances. X-ray shadow image of a small object 55Fe measurement Shadow of 16 m thick golden bonding wire 16µm Pixel matrix (32x256)

Four transistor pixels The pixel electronics is based on 4 PMOS transistors, the pixel output signal is current. The readout is of rolling-shutter type, the column signals are compensated for offsets on the chip using 8-bit DACs and compared with a threshold. 1.1 V Reset V. Res Res 1.1 V Sensor diode Sel Out 2.5 µm

Complementary “smart diode” Complementary structure – “smart” Pwell in Nwell diode (electronics based on NMOST) Only the charge generated in the depleted region of a thickness 2.5-5 µm near the chip surface are collected. Reduced charge sharing NMOS 4 µm 2.5 µm Collected 6.5 µm Not collected 20-50V

Development for the transmission electron microscopy

HPIXEL HPixel: an HVCMOS detector with small pixels (25x25 µm) in 180nm AMS HV-technology. The readout is of rolling-shutter type. The detector has been successfully tested using various radioactive sources. The signal and noise have been estimated.

Integrating pixels with CDS Correlated double-sampling (CDS) is implemented in the pixels using CMOS electronics. The pixel output signals are digitized by 128 on-chip ADCs. The readout electronic has been optimized for a fast readout and a low power consumption. 25 µm VP VP Res Sample Res Sel Sel Sel Out

Integrating pixels with CDS Correlated double-sampling (CDS) is implemented in the pixels using CMOS electronics. The pixel output signals are digitized by 128 on-chip ADCs. The readout electronic has been optimized for a fast readout and a low power consumption. 25 µm VP VP Res Signal l. Sample Res Sel Reset l. Sel Sel Reset level

Integrating pixels with CDS Correlated double-sampling (CDS) is implemented in the pixels using CMOS electronics. The pixel output signals are digitized by 128 on-chip ADCs. The readout electronic has been optimized for a fast readout and a low power consumption. 25 µm VP VP Res Signal l. Sample Res Sel Signal l. Sel Sel Signal level

Integrating pixels with CDS Correlated double-sampling (CDS) is implemented in the pixels using CMOS electronics. The pixel output signals are digitized by 128 on-chip ADCs. The readout electronic has been optimized for a fast readout and a low power consumption. 25 µm VP VP Res Sample Res Sel Reset l. Sel Sel

Integrating pixels with CDS Correlated double-sampling (CDS) is implemented in the pixels using CMOS electronics. The pixel output signals are digitized by 128 on-chip ADCs. The readout electronic has been optimized for a fast readout and a low power consumption. 25 µm VP VP Res Sample Res Sel Reset l. Sel Sel Irradiation

Thank you

Backup slides

Measurements with a test pad FEI4 HVCMOS Injection Test pad

Measurements with a test pad 0.577V -> 2964e => Capacitance = 0.824fF Calibrated input: FEI4 noise 73e (FEI4 threshold was set to 1300e)

Technology issues – sensor capacitance Relatively large size of the collecting electrode. The high-voltage bias reduces the problem. Example – large pixels for ATLAS: 110 μm 15μm 10 μm C_area = 0.148fF/μm2 P-well C_area = 0.015fF/μm2 C_sw = 0.385fF/μm C_sw = 0.18fF/μm N-well ~30fF 60V ~70fF Total :100fF

Technology issues – crosstalk Capacitive feedback into the sensor (n-well) Many important circuits do not cause problems: charge sensitive amplifier, simple shaper, tune DAC, SRAM but… “Active” (clocked) CMOS logic gates and sometimes comparators cause large crosstalk Possibility 1: Implement the circuits only using NMOST: effects on radiation tolerance, layout area, power consumption, etc. Possibility 2: Place the active digital circuits on the chip periphery or on separate chip. Possibility 3: Isolate PMOST from n-well using an additional standard technology feature – the deep P-well – we still haven’t tested it… 1.8v 1.8v PMOS NMOS NW or SN PW DP DN PSUB

„HVMAPS“ – HVCMOS or SDA CMOS pixel flavors CMOS pixel flavors: Standard MAPS INMAPS „HVMAPS“ – HVCMOS or SDA TWELL MAPS

HV CMOS detectors Collected charge causes a voltage change in the n-well. This signal is sensed by the amplifier – placed in the n-well. P-substrate PMOS NMOS G holes S D electrons N-well P-well

HV CMOS detectors Collected charge causes a voltage change in the n-well. This signal is sensed by the amplifier – placed in the n-well. P-substrate

HV CMOS detectors Collected charge causes a voltage change in the n-well. This signal is sensed by the amplifier – placed in the n-well. P-substrate

HV CMOS detectors Charge sharrng due to diffusion PMOS NMOS deep n-well Drift 60V ~15µm Depletion zone

PMOS isolation 180 nm technology PMOS STI - FOX SN DP DN

PMOS isolation 180 nm technology PMOS STI - FOX SN DP Short??? DN

Drawbacks 350 nm technology PMOS LOCOS - FOX SN DP DN

Complementary structure for TEM Complementary structure – smart Pwell in Nwell diode (electronics based on NMOST) Only the charge generated in the depleted region of a thickness 2.5-5 µm near the chip surface are collected. Reduced charge sharing. 2.5 µm NMOS P-substrate N-well P-well