Technical University Tallinn, ESTONIA Overview: Fault Simulation Overview about methods Low (gate) level methods Parallel fault simulation Deductive fault simulation –Gate-level fault lists propagation (library based) –Boolean full differential based (general approach) –SSBDD based (tradeoff possibility) Concurrent fault simulation Critical path tracing Parallel critical path tracing Hierarchical fault simulation

Technical University Tallinn, ESTONIA Faults in Digital Circuits 0110 T FaultF 5 located Fault table Test experiment Test generation Fault simulation Fault diagnosis Fault modeling Testing How many rows and columns should be in the Fault Table?

Technical University Tallinn, ESTONIA Fault simulation Goals: Evaluation (grading) of a test T (fault coverage) Guiding the test generation process Constructing fault tables (dictionaries) Fault diagnosis Generate initial T Evaluate T Sufficient fault coverage? Modify T Done YesNo Select target fault Generate test for target Fault simulate Discard detected faults Done No more faults Deterministic test generation Random test generation

Technical University Tallinn, ESTONIA Fault simulation Fault simulation techniques: serial fault simulation parallel fault simulation deductive fault simulation concurrent fault simulation critical path analysis parallel critical path analysis Common concepts: fault specification (fault collaps) fault insertion fault effect propagation fault discarding (dropping) Comparison of methods: Fault table Faults F i Test patterns T j Entry (i,j) = 1(0) if F i is detectable (not detectable) by T j

Technical University Tallinn, ESTONIA Single and Parallel Fault Simulation Parallel patterns Fault-free circuit: Faulty circuit: & 1 x1x1 x2x2 x3x3 z y & 1 x1x1 x2x2 x3x3 z y Inserted stuck-at-1 fault Detected error Fault-free circuit: Faulty circuit: & 1 x1x1 x2x2 x3x3 z y & 1 x1x1 x2x2 x3x3 z y Inserted stuck-at-1 fault Detected error Three test patterns Single pattern

Technical University Tallinn, ESTONIA Critical Path Tracing & & a c b y y Problems : & & /01/0 y & & y 1/ The critical path is not continuous The critical path breaks on the fan-out

Research in ATI © Raimund Ubar Algorithm: 1.Determine the activated path to find the fault candidates 2.Analyze the detectability of the each candidate fault (each node represents a subset of real faults) Fault Analysis with SSBDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x & & & 1 & x1x1 x2x2 x3x3 x4x4 y x11x11 x 21 x12x12 x 31 x13x13 x 22 x

Research in ATI © Raimund Ubar 8 Properties of SSBDDs Property 2: If a test vector X activates in SSBDD a 0-path (1-path) which travers a subset of nodes M, then only 0-nodes (1-nodes) have to be considered as fault candidates Speeding-up simulation: M = {1,2,3,4,6,7} M* = {1,6,7} – by Property 2 M** = {6,7} – by Property 1 Fault diagnosis and fault simulation can be speed-up by using Property 2 Only 6 and 7 have to be considered Fault diagnosis / Fault simulation: y y

Technical University Tallinn, ESTONIA Parallel Critical Path Tracing & 1 x1x1 y Detected faults vector: T1: No faults detected T2: x 1  1 detected T3: x 1  0 detected T4: No faults detected x3x3 x2x2 Handling of fanout points: Fault simulation Boolean differential calculus x y xkxk x2x2 x1x1 F

Technical University Tallinn, ESTONIA Parallel Critical Path Tracing Problem with fan-out points:

Technical University Tallinn, ESTONIA Parallel Critical Path Tracing Problem with sequentiality: F1F1 R6R6 R1R1 R2R2 R7R7 X1X1 X2X2 X3X3 F2F2 F3F3 F4F4 R8R8 R4R4 R5R5 R3R3 X4X4 F5F5 F7F7 F8F8 F6F6 R 10 X5X5 R9R9 Y2 Y1 Z1Z1 Z2Z2

Technical University Tallinn, ESTONIA Parallel Critical Path Tracing Problem is solved: Two reasons why a fault can be propagated to the same component during different time frames: global feedback, fan-outs with re-convergence in different time frames MISR can be connected to these “problem causing” test points The fault will be captured at the first occasion. The detection of the fault will be fixed, and we can ignore its impact in the future

Technical University Tallinn, ESTONIA Overview: Fault Diagnosis Combinational methods of diagnosis –Fault table based methods –Fault Dictionary based methods –Minimization of diagnostic data in fault tables –Methods for improving the diagnostic resolution Sequential methods of diagnosis –Edge-Pin testing –Guided Probe fault location Fault diagnosis with Boolean Differentials Physical Defect Diagnosis Design error diagnosis

Technical University Tallinn, ESTONIA Combinational Fault diagnosis 0110 T FaultF 5 located FaultsF 1 andF 4 are not distinguishable Fault localization by fault tables No match, diagnosis not possible

Technical University Tallinn, ESTONIA Combinational Fault Diagnosis Fault dictionaries contain the sama data as the fault tables with the difference that the data is reorganised The column bit vectors can be represented by ordered decimal codes or by some kind of compressed signature Fault localization by fault dictionaries

Technical University Tallinn, ESTONIA Sequential Fault Diagnosis Sequential fault diagnosis by Edge-Pin Testing Diagnostic tree: Two faults F 1,F 4 remain indistinguishable Not all test patterns used in the fault table are needed Different faults need for identifying test sequences with different lengths The shortest test contains two patterns, the longest four patterns

Technical University Tallinn, ESTONIA Sequential Fault Diagnosis Guided-probe testing at the gate level Searh tree: Faulty circuit

Technical University Tallinn, ESTONIA Improving Diagnostic Resolution Method: F1 may influence both outputs, F2 may influence only x 8 A test pattern 0010 activates F1 up to the both outputs, and F2 only to x 8 If both outputs will be wrong, F1 is present If only x 8 will be wrong, F2 is present Generating tests to distinguish faults F1: x 3,1  0 Faults are influencing on different outputs: x 2 x 3 x 4 x 3,1 x 3,2 x 5 x 6 x 7 x  1 x F2: x 4  1

Technical University Tallinn, ESTONIA Improving Diagnostic Resolution Method: Both faults influence the same output of the circuit One of them should be blocked Two possibilities: A test pattern 0100 activates the fault F2. F1 is not activated: the line x 3,2 has the same value as it would have if F1 were present A test pattern 0110 activates the fault F2. F1 is now activated at his site but not propagated through the AND gate Generating tests to distinguish faults F1: x 3,2  0 F2: x 5,2  1 How to activate a fault without activating another one? x 5,1 x 5,2 x 2 x 3 x 4 x 3,1 x 3,2 x 5 x 6 x 7 x  1 x /1 0

Technical University Tallinn, ESTONIA Improving Diagnostic Resolution Method: Both of the faults may influence only the same output Both of the faults are activated to the same OR gate, none of them is blocked However, the faults produce different values at the inputs of the gate, they are distinguished if x 8 = 0, F1 is present otherwise, if x 8 = 1 (OK value) either F2 is present or none of the faults are present Generating tests to distinguish faults F1: x 3,1  1 How to activate a fault without activating another one? x 5,1 x 5,2 x 2 x 3 x 4 x 3,1 x 3,2 x 5 x 6 x 7 x  1 x F2: x 3,2  1

Research in ATI © Raimund Ubar 21 Boolean Differentials and Fault Diagnosis dx - fault variable, dx  (0,1) dx = 1, if the value of x has changed because of a fault Partial Boolean differential (for fault simulation): Full Boolean differential (for fault diagnosis):

Research in ATI © Raimund Ubar Boolean Differentials and Fault Diagnosis x 1 = 0 x 2 = 1 x 3 = 1 dy = 0 Diagnostic experiment : Test pattern - Correct reaction Adjusting for SAF faults: Substitution of values: Partial diagnosis: 22

Research in ATI © Raimund Ubar Boolean Differentials and Fault Diagnosis x 1 = 0 x 2 = 1 x 3 = 1 dy = 0 1) Correct output signal : 2) Erroneous output signal : x 1 = 0 x 2 = 0 x 3 = 0 dy = 1 Two diagnostic experiments : Diagnosis from two experiments : 23

Research in ATI © Raimund Ubar Boolean Differentials and Fault Diagnosis = 0 Final diagnosis: The line x 3 works correctly There is a fault: The fault is missing Rule: Diagnosis from two experiments : 24 Rule: