1 Timing System Timing System Applications

2 Timing System components Counting mechanisms Input capture mechanisms Output capture mechanisms

3 Counting system 16-bit unsigned counter (TCNT) incremented at a fixed rate determined by two programmable bits (PR1 and PR0). The counter cannot be stopped or reset. For an E clock of 2 MHz (= 500 ns period)

4 Input Capture System The 68HC11 has 3 input capture modules: Each input Capture module has: And external input pin IC n A flag bit Two edge control lines An interrupt mask bit A 16-bit input capture register There are no directions register bits associated with PA2-0, These bits are always inputs

5 Input Capture basic structure

6 Actions occurring as a result of a capture event 1. The current TCNT value is copied into the input capture register (TIC n ) 2. The input capture flag is set (IC n F) 3. If the mask bit is armed (ICI n set to 1) an interrupt is requested

7 Input Capture Registers

8 Input Capture modes IC1IC2IC3

9 Input Capture flags When an input capture event (edge) of the type activated (TCTL2 reg.) occurs on the IC pin the corresponding input capture flag is set (IC1F, IC2F, IC3F) and the current value of TCNT is stored in the corresponding timer control register (TIC1, TIC2, TIC3). Every time TCNT overflows from $FFFF to $0000, the TOF flag is set The software can determine if an input capture event occurred by reading the flag registers

10 Input Capture flags The flags are cleared by writing a 1 into the specific flag bit we wish to clear Do not use bset or TFLG1 |= 0x01 (no read-modify-write operations !) If for example we had 0xFF in TFLG1 as a result of the OR we end up writing 0xFF in TFLG1 so we clear all the flags instead of the LSB only) ldaa #$01 staa $1023 TFLG1=0x01 example

11 Input Capture masks If the input capture flags are armed (IC1I, IC2I, IC3I, TOI) then an interrupt will be requested as soon as the flag is set Interrupt mask for the TOFTCNT rate

12 Input Capture Applications Arm the flag bit so that an interrupt is requested on the active edge of an external signal Perform two rising edge input captures and subtract the two measurement to get period Perform a rising edge capture then a falling edge capture, and subtract the two measurements to get pulse width …

13 Real Time interrupt using Input Capture x C T x (R A +2R B ) Example: Create a periodic interrupt (one interrupt every ms). Every time there is the interrupt we increment a global variable TIME

14 Real Time interrupt using Input Capture There is a latency between the rise edge of the interrupt and when the increment of TIME really occurs: (1) finish the current instruction (2) process the interrupt (3) execute the interrupt handler (including changing TIME) 6811 Longest instruction: 41 cycles Process the interrupt: 14 cycles Execute handler: 28 cycles (our code) Max latency:83 cycles (=41.5  s)

15 Real Time interrupt using Input Capture The interrupt software: (1) performs a poll (check the flag), (2) acknowledge the interrupt (clear the flag), (3) increments the global variable set IC3 to be active on pos. edge and leave the others alone make sure the interrupt flag for IC3 is clear arm IC3 interrupt and leave the others alone make sure the execution of the initialization software cannot be interrupted

16 Real Time interrupt using Input Capture If we jumped to the interrupt routine and the flag is not set then there is an ERROR !! Total 28 Poll the flag

17 Real Time interrupt using Input Capture

18 Period Measurement Resolution smallest change in period that can reliably be measured Precision number of separate and distinguishable measurements that we can take (e.g  16 bits) Range The minimum and maximum values that can reliably be measured

19 16-bit period measurement with 500 ns resolution using input capture The period is calculated as the difference in TIC1 values from on rising edge to the other This method does not operate properly if the period is larger than cycle The shortest period that can be handled is given by: num. cycles to process the interrupt + num. cycles of the handler The resolution is 500 ns because the period must increase of at least this amount before the difference between TIC1 measurements can be appreciated +V -V

20 32-bit period measurement with a 500 ns resolution using input capture Every time the TCNT overflows from $FFFF to $0000, the TOF flag is set. We can increase the precision of the period measurement by counting the number of TOF flag setting events during one period

21 Pulse-width measurements The basic idea is to cause an input capture event on both the rising and falling edges of an external signal

22 Pulse width measurement using busy waiting T = 0.45  (R+R1)  C We chose R1 and C so that the resistance range 0  R  1M  maps into 500 ns  T  1000  s  T = 0.45   R  C   T=500 ns   R=1K  Multivibrator

23 Pulse width measurement using busy waiting

24 Pulse width measurement using busy waiting

25 Pulse width measurement using interrupts Both the rising and falling edges will generate an input capture interrupt IC1 Rising = TIC1PW = TIC1 - Rising

26 Pulse width measurement using two input capture channels The lower bound on the range is determined by the software overhead to process the input capture interrupt The rising edge time will be measured by IC2 without the need of an interrupt routine, and the falling edge interrupt will be handled by IC1

27 Output compare system Each output compare module has: An external output pin OC n A flag bit A force output compare control bit FOC n Two control bits (OM n, OL n ) An interrupt mask bit A 16-bit output compare register The 68HC11 has 5 output compare modules There is a direction register bit for PA7/OC1 (DDRA7 bit in PACTL) and a direction register bit for PA3/OC5 (DDRA3 bit in PACTL)

28 Output compare basic structure

29 Actions occurring as a result of an output compare event An output compare event occurs when either: The 16-bit TCNT matches the the 16-bit OC register The software writes a 1 to the FOC bit As a result of an output compare event: 1. The OC n output signal change 2. The output compare flag OC n F is set 3. If the mask bit OC n I is armed an interrupt is requested

30 Output compare registers

31 Output compare modes and levels The TCTL1 register determines what effect the output compare event will have (none, toggle, clear, set) on the output pins (OC1, OC2, OC3, OC4, OC5)

32 Output compare flags The software can determine if an output compare event occurred by reading the flag registers The flags are cleared by writing a 1 into the specific flag bit we wish to clear

33 Output compare mask If the output compare flags are armed (OC1I, OC2I, OC3I, OC4I, OC5I, TOI) then an interrupt will be requested as soon as the flag is set Interrupt mask for the TOFTCNT rate

34 The pulse accumulator mechanism The output compare OC1, operates differently. It can also be used as pulse accumulator mechanism. On a successful OC1 event (TCNT=TOC1), the microcontroller can be programmed to set or clear any of the OCn pins. OC1M tells which pin(s) will be affected by the OC1 event OC1D specify the reulting value of the output pin(s) after an OC1 event

35 Output compare applications create square waves create variable duty cycles waveforms generate pulses implement time delays execute periodic interrupts …

36 Fixed Time Delay fixed is the number of cycles you wish to wait 1. read the current 16-bit TCNT 2. calculate TCNT + fixed 3. set the 16-bit output register to TCNT + fixed 4. clear the output compare flag 5. wait for the output compare flag to be set

37 Periodic interrupt using output compare Increments a global variable Time every 1 ms 2000 x 500 ns = 1ms

38 Square wave generator Fastest square waveform  2 × Total execution time Total execution time = time to process the interrupt + time to execute the handler for the 68HC11 is 14 cycles

39 Square wave generator OM3 = 0, OL3 =1 Toggle output OC3

40 Pulse Width Modulation Average Current (= DC current) Effective and popular mechanism for embedded systems to control external devices

41 Pulse Width Modulator duty cycle = high / (high + low)

42 Pulse Width Modulator

43 Pulse Width Modulator

44 Pulse Width Modulator Process interrupt: 14 cycles Execute handler: cycles Total Time T: cycles Both High and Low must be bigger than T

45 Delayed pulse generation Use the pulse accumulator Disarm so that the output pulse occurs only once not every counts of TCNT

46 Frequency Measurement Basic idea: count the number of input pulses occur for a fixed amount of time Use input capture to count the pulses Use output capture to create the fixed time interval counter fixed time f = frequency resolution =  f = 1 fixed time