Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France Calorimeter upgrade meeting Olivier Duarte Upgrade calo FE review Comments : Digital part Friday, 20 September 2013 This is just a support to start the discussion

Olivier Duarte FPGA Choice 2  Point (2) :  Open questions on the architecture of the FEB and the CB  a single FPGA could do the job of the "Trigger-PGA" and the job of the "Control-PGA”  New target SmartFusion2 flash FPGA from MicroSemi  At the moment we target A3PE 1500 FPGA for the FEPGA of the FE block (FEB). It’s a compromise between radiation tolerance, price, number and standart IOs and internal resource in the chip.  A single FPGA for “Trigger and Control” Why not ! It will be define when we define precisely the architecture of the board !  The new family FPGA SmartFusion2 include specifiques functions as SerDes, Arm processor, etc (We haven’t need of the function !). But “Buffers Implemented with SEU Resistant Latches on the DDR bridge SPI FIFO”. Price and availability?  Need more investigation on this new family ! Friday, 20 September 2013 Calorimeter upgrade meeting

Olivier Duarte SLVS-LVDS translation 3  Point (3) :  The need for SLVS-LVDS translation must be evaluated. The GBTX is specified to receive LVDS signals. Basic tests from CMS indicate that the A3PE1500 can accept SLVS signals, but these should be verified with more detailed tests.  The prototype FEB and CROC board will be used to test this compatibility of the A3PE and SLVS Friday, 20 September 2013 Calorimeter upgrade meeting

Olivier Duarte Clock distribution on the backplane 4  Point (6) :  The clock distribution architecture in the FEB crate should be investigated.  Usage of buffers or translators within FPGAs might create additional jitter or destroy fine phase/latency control.  If it is possible to go directly from the GBTX chip to the FPGA or analog chip via the backplane (with no significant degradation of signal in terms of jitter) than that should be the cleanest option.  On the board it’s possible to go directly from the GBTX chip to the FPGA.  On the backplane we will used LVDS, It will be tested with the prototype board (FEB and CROC)  Even if we want to use SLVS on backplane, it’s necessary to use buffer (vey low jitter!) between the board and the backplane. Friday, 20 September 2013 Calorimeter upgrade meeting

Olivier Duarte First prototype with mezzanine for GBTX and SCA 5  Point (7) :  It was suggested to design the first prototypes to have mezzanines or similar so that external chips (GBT-SCAs or GBTXs) can be plugged when available and tests can still be performed while waiting for those chips to be available.  The idea is to do the prototype FEB and CROC with the footprint describe in the GBT datasheet (BGA)  Very difficult to implement a mezzanine (area, type of connectors,...)  It’s possible to start the tests of the board without GBT solder on the PCB ! Friday, 20 September 2013 Calorimeter upgrade meeting

Olivier Duarte No mezzanine for data transmission 6  Point (8) :  In the initial version of the new design, event data serializers and associated optical drivers were located on mezzanines. Due to the lack of manpower for following this option, it might be wise to come back to a direct implementation of these components on the front-end boards.  Increase the intrinsic cost of the front-end boards  No mezzanine, event data serializers and asociated optical drivers will be located on the FEB and on the CROC.  To separate the cost of the links (serializers + optical drivers/receivers + fiber optics) from that of the boards and to have a separate funding  See Frédéric Friday, 20 September 2013 Calorimeter upgrade meeting

Olivier Duarte Firmware download by Slow Control 7  Point (10) :  In-situ programming of the FPGAs should be investigated in more detail. This assumes that the bit-stream can be transmitted via the GBT-SCA.  The power requirements for the flash programming should be clarified and incorporated into the system.  Completely agree with this point  In fact we want to reuse and adapt the development of the CMS team  What is the situation of this development ?  Completely agree with this point Friday, 20 September 2013 Calorimeter upgrade meeting

Olivier Duarte Spare 8 Friday, 20 September 2013 Calorimeter upgrade meeting

Olivier Duarte Front-end board global architecture Detector cells 9

Olivier Duarte Front-end Board architecture 10 New FEB 32 Channels Clk manager Clk[7:0] In Ref Down- link Uplink General Ctrl GBTX E-Port ACTEL FPGA (A3PE1500) LVS-SLVS translator 4 GBTX (One way) Analog FE part (8 Channels) E-Port SCA Network Controller User Buses : {I2C, //, SPI, JTAG, 12bADC, …} Translator SLVS-LVDS FPGA, Buffer, … 4 One way link per FEB for DAQ  GBT on board On the new Calorimeter FEB 4 GBTX chip (one way) for Data 1 GBTX chip (one way) for LLT 1 SCA chip (FEB Ctrl/Cmd)  Technology Analog Front-end ASICS (Barcelona) Discret components solution Digital Part Actel FPGA, A3PE family Clock_Feb(n) Clock from CROC Through backplane Slow control from CROC Through backplane PM 1 One way link per FEB for LLT April 10th 2013

Olivier Duarte CROC architecture 11  GBT on board On new CROC board 2 GBTX (one master) chip with bidirectional optical fiber (right side and left side of FE crate) 1 SCA chip (CROC Ctrl/Cmd)  Why keep the CROC Provide the distribution of the synchronous commands signal (Channel B, …) to the FEB inside FE Crate Provide Slow Control distribution Provide Clk distribution New CROC Clk manager Clk[7:0] In Ref Down- link Uplink General Ctrl GBTX E-Port 2 GBTX E-Port SCA Network Controller User Buses : {I2C, //, SPI, JTAG, 12bADC, …} 1 SCA SLVS-LVDS translator Buffer Clk[0] 2 bidir link E-Port SCA _NewCROC E-Port SCA_NewCROC E-Port_FEB E-Port_TVB x (18) Translator SLVS-LVDS FPGA, Buffer, … One GBTX master Clock distribution to FEB through backplane 2 bidir link LHCb AMC40 firmware workshop April 10th 2013