Power Integrity: A Nanoscale VLSI Challenge Raj Nair, Anasim Corporation Oct. 2, 2008

October 2008 © 2008 AnaSIM 2 Overview Scaling & its less-known L*di/dt challenge Scaling & its less-known L*di/dt challenge The Power Wall, breaking through The Power Wall, breaking through True-Electromagnetic PI analysis True-Electromagnetic PI analysis Energy & Noise Management Energy & Noise Management Non-disruptive Scaling Non-disruptive Scaling Summary Summary

October 2008 © 2008 AnaSIM 3 Scaling Progression

October 2008 © 2008 AnaSIM 4 Planar CMOS transistor Scaling A lower Energy*Delay*Cost product… but challenges led to a severe Power Wall

October 2008 © 2008 AnaSIM 5 Scaling Challenge: CPU Chip PI Power doubles every ~36 months Transistors double every ~18 months Operating modes create load shifts Which create supply voltage ‘droops’ Managed by package devices (Original figure from C. Baldwin) Mother Board Capacitors Microprocessor Heat Spreader Package Substrate Pentium™ is a trademark of Intel® Corporation

October 2008 © 2008 AnaSIM 6 Package CAP Loop-L scaling and gives Load shift induced voltage noise equation and derivation of package component characteristics scaling Inversely related to process scaling (on-die cap) & (freq. scaling) 2 65nm <<0.1pH! References: Nair 2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’ 2002 Intel Technology Journal paper “Emerging Directions for Packaging…”Emerging Directions for Packaging

October 2008 © 2008 AnaSIM 7 On-die L & L*di/dt challenge References: Nair, Nair & Bennett, 2008 EDADesignline® publications “A Power Integrity Wall follows the Power Wall” & “Dynamic Voltage Droops & Total PI”A Power Integrity Wall follows the Power WallDynamic Voltage Droops & Total PI

October 2008 © 2008 AnaSIM 8 The Power Wall ’71’74’78’85’92’00’04’08 Power (Watts) Pentium™ processors Processor power doubles every ~36 months… References: Nair 2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’ 2002 Intel Technology Journal paper “Emerging Directions for Packaging…”Emerging Directions for Packaging CPU power is now capped or reducing in Multi-Core, SoC Architectures Pentium™ is a trademark of Intel® Corporation

October 2008 © 2008 AnaSIM 9 Scaling into the Nanoscale Era Drain induced barrier lowering in short channel devices makes leakage increase with Vds (V-Supply) Sub-threshold channel leakage dominates V-supply dependent leakage. Source: Narendra & Chandrakasan Leakage in Nanometer Technologies, Springer Publications, 2005 Greater challenges… High-K is only a partial solution

October 2008 © 2008 AnaSIM 10 Power, Performance, Leakage Power Power Active power estimated as (P=  CV 2 f), V   P  Active power estimated as (P=  CV 2 f), V   P  With supply-V scaling, V T must scale for performance With supply-V scaling, V T must scale for performance Leakage Leakage I OFF  10  е (  V T /S), and S ~= 85mV/decade I OFF  10  е (  V T /S), and S ~= 85mV/decade I OFF rises 10X with 85mV reduction in V T I OFF rises 10X with 85mV reduction in V T Short channel barrier lowering (DIBL, )  I OFF  Short channel barrier lowering (DIBL, )  I OFF  Source: S. Narendra, Tyfone, Inc.

October 2008 © 2008 AnaSIM 11 Power Trend Reference: Narendra, ICCAD ‘03 Leakage power now equals active power!! Both strongly dependent upon supply voltage.

October 2008 © 2008 AnaSIM 12 Performance w/ Voltage Scaling I DS  (V GS  V T )  I DS  (V GS  V T )  Linear dependence in deep nanoscale CMOS Linear dependence in deep nanoscale CMOS Delay & Frequency Delay & Frequency C  V dd /I ds ~constant C  V dd /I ds ~constant Nanoscale CMOS delay and performance are roughly constant within a ΔV dd range of V dd Nanoscale CMOS delay and performance are roughly constant within a ΔV dd range of V dd Opportunity Opportunity Use lowest possible V dd ! Use lowest possible V dd ! Chau et al., IEDM 2000 Accurate supply noise estimation a must } } }

October 2008 © 2008 AnaSIM 13 Voltage Minimization is Key Total power strongly V-dependent Total power strongly V-dependent Active power proportional to V 2 Active power proportional to V 2 Leakage (tunneling) also related as V x (DIBL, E- field, tunneling distance reduction with V) Leakage (tunneling) also related as V x (DIBL, E- field, tunneling distance reduction with V) Energy / task minimized similarly Energy / task minimized similarly ΔI DS ~linearly related to ΔV in nanoscale processes ΔI DS ~linearly related to ΔV in nanoscale processes How low can you go? How low can you go? Digital: supply gating Digital: supply gating Analog: fine grain supply voltage control Analog: fine grain supply voltage control Need accurate noise, power integrity estimation Need accurate noise, power integrity estimation Reference: Nair, AZ Nanotechnology Symposium 2006

October 2008 © 2008 AnaSIM 14 Supply Noise Analyses Examples Chip grid IR drop analysis Power Grid == Resistance Package simulation Chip == current source Are these the high levels of approximation (for design optimization) desirable??

October 2008 © 2008 AnaSIM 15 On-Chip Analysis Challenge Atomic or Abstract? Atomic or Abstract? Analyze supply surface ripples by ‘molecular’ interactions? Polygonal Analyses Polygonal Analyses Nanoscale IC’s today face exploding computational complexity (R, L, C, I, dI) Energy & Efficiency Energy & Efficiency Must know IC’s supply ripples for optimization

October 2008 © 2008 AnaSIM 16 Meeting the Challenge Differential Power Differential Power Voltage is a potential difference; treat power grid differentially Partition hierarchically & exploit symmetry ECD: Continuum models ECD: Continuum models Grid is uniform; treat as a voltage-continuum along a single surface USPTO PUBUSPTO PUB Include R, L, C and solve ‘true-electromagnetically’ Abstract silicon, package Abstract silicon, package Include distributed models for silicon loads, CAP, pkg and board components

October 2008 © 2008 AnaSIM 17 Abstraction & Physics-based Sims High levels of Abstraction High levels of Abstraction Power GRID as SURFACE Power GRID as SURFACE DISTRIBUTED circuit load currents & capacitance DISTRIBUTED circuit load currents & capacitance SYMMETRY in physical as well as electrical aspects SYMMETRY in physical as well as electrical aspects Comprehensive Modeling Comprehensive Modeling All grid electromagnetic properties, R, L, C used All grid electromagnetic properties, R, L, C used Actual block load current profiles used; di/dt, load activity factors included Actual block load current profiles used; di/dt, load activity factors included Physics based Simulation Physics based Simulation Field solver employed for Maxwell’s equations on ‘surfaces’ / NO ‘models’ Field solver employed for Maxwell’s equations on ‘surfaces’ / NO ‘models’

October 2008 © 2008 AnaSIM 18 On-Die CAP for Noise Reduction Simple, lumped SPICE analyses indicate On-Die CAP helps in ΔV CC reduction Area cost, Gate Oxide leakage are concerns Reference: Narendra, ICCAD ‘03

October 2008 © 2008 AnaSIM 19 SoC Power Integrity Simulation Do CAPACITORS (reactive devices) really absorb/expend noise energy? 9 x 7mm chip 5nF /sq. cm distributed CAP 100mA peak noise pulse of 100ps width Power grid simulation Explicit CAP LENS Pulse noise source Differential noise R+L+C Dynamic Noise Simulation in  -fp Source: D. Bennett, ANASIM Corp.,  -fp power integrity aware floor planner, Animation slide Use slide show

October 2008 © 2008 AnaSIM 20 Single active circuit block in a 4x4mm IC   -fp ‘what-if’ experiments showing effect of gate switching time and on-chip de-cap on maximum voltage droop. resonance Resonant effects; More / Less CAP?

October 2008 © 2008 AnaSIM 21 CAP Connectivity & Noise CAPACITOR blocks from IO ring corners connected into Core power grid increased noise in the core grid Corner CAPs connected to IO RingCorner CAPs connected to Core Grid Analysis on a CLOCK chip Source: ANASIM Corp.,  -fp power integrity aware floor planner,

October 2008 © 2008 AnaSIM 22 SoC Power Grid a Noise Conduit Low impedance grids conduct and sum up supply noise Low impedance grids conduct and sum up supply noise Low energy loss in global power grids  more, sustained noise Low energy loss in global power grids  more, sustained noise Scaling and high perf.  high local di/dt & loop inductance leads to greater local noise Scaling and high perf.  high local di/dt & loop inductance leads to greater local noise Reference: Bennett, EEDesign 2003 article, Animation slide

October 2008 © 2008 AnaSIM 23 Power Gating & Noise Flow Source: ANASIM Corp.,  -fp power integrity aware floor planner, Power Gating transforms preferred pathways for noise flow in addition to transient noise generation due to large switched capacitances… Animation slide

October 2008 © 2008 AnaSIM 24 Example: System-level Chip Sim GUI or Netlist capture GUI or Netlist capture Chip NETLIST Chip NETLISTNETLIST Load current profiles are pulse100gap100 and pulse200gap200 Load current profiles are pulse100gap100 and pulse200gap200 pulse100gap100 pulse200gap200 pulse100gap100 pulse200gap200 SYMMETRY in physical as well as electrical aspects SYMMETRY in physical as well as electrical aspects Experiment-1 results Experiment-1 results Chip grid ANIMATION & Mirror Chip grid ANIMATION & MirrorANIMATION MirrorANIMATION Mirror Notice substantial voltage variation of top left corner Notice substantial voltage variation of top left corner Cap 200pF added: results Cap 200pF added: results Chip grid ANIMATION & Mirror Chip grid ANIMATION & MirrorANIMATION MirrorANIMATION Mirror  -fp simulation schematic illustration (hyperlinked image)

October 2008 © 2008 AnaSIM 25 Chip Grid R, L + C Design  With fixed on-chip capacitance value, increase in grid wire width (reduction in resistance with minimal benefit in inductance) reduces noise to a point  Increase in capacitance on-die has sub-linear benefit in noise reduction; more CAP is not always good…

October 2008 © 2008 AnaSIM 26 How does it help design? bridges the PI gap  -fp bridges the PI gap  -fp  Complements IR Drop traditional IC analysis with true-electromagnetic sims  Energy : Optimizes supply voltage domain levels  Optimizes power grids; front-end CAP planning  Reduces cost : Routing, Chip Area, Design Effort  System-Level analysis Minimizes costly design iterations

October 2008 © 2008 AnaSIM 27 Dynamic Energy Management Power  Performance, Energy  Battery Life Power  Performance, Energy  Battery Life Power & Energy Power & Energy Task completion at low power with low frequency, but same energy (P  T)  Must minimize voltage! Circuits/Design in SoC’s Circuits/Design in SoC’s Adaptive Voltage Scaling, Dynamic Voltage scaling PowerWise™ compliant example in figure Benefits in V-domains Figure source: Mobile Handset Designline How To, 2007 Learning from CPUs’ VID bus and Adaptive Voltage Positioning for Power Integrity

October 2008 © 2008 AnaSIM 28 External Voltage & Noise Control Distributed Local Voltage Regulation Distributed Local Voltage Regulation Multiplies bandwidth: smaller the regulator, faster it can be Local placement ensures low latency, high loop bandwidth Decentralized, simple, hardware energy management design Issues: Component testing Stacked Active Passives Integration (SAPI) Stacked Active Passives Integration (SAPI) Non-disruptive, practical and low-cost References: Nair, US Patents , , , USPTO publication , US Patent

October 2008 © 2008 AnaSIM 29 Prescott-CPU ANR Inclusion Reference: Intel® Prescott CPU-PKG simulation model, ComLSI ANRComLSI ANR

October 2008 © 2008 AnaSIM 30 Prescott Pre-ANR Nom. VDD

October 2008 © 2008 AnaSIM 31 Prescott Post-ANR Nom. VDD No spatial info, V as f(x,y,t)

October 2008 © 2008 AnaSIM 32 Advanced SiP Simulation Near load systems Near load systems Active Noise Regulator* Active Noise Regulator* Distributed Local (POL) Voltage Regulators Distributed Local (POL) Voltage Regulators Spatial & Temporal Spatial & Temporal Power supply variation in x, y and t Power supply variation in x, y and t Data can feed into future Dynamic Timing Analysis? Data can feed into future Dynamic Timing Analysis? Simulation speed allows ‘what-if’ experiments for optimization Simulation speed allows ‘what-if’ experiments for optimization Chip power grid noise ANR attached to top left corner of grid Reference: * Nair & Bennett, ComLSIComLSI Power Management Designline article Animation slide Use slide show

October 2008 © 2008 AnaSIM 33 Managing Leakage Power Classical techniques Classical techniques Dual or Multi-V T processes Dual or Multi-V T processes High-K gate oxide High-K gate oxide SLEEP Transistors (gate-level) SLEEP Transistors (gate-level) Threshold voltage modulation Threshold voltage modulation Adaptive Body Bias / Dynamic Body Bias Adaptive Body Bias / Dynamic Body Bias Supply voltage modulation Supply voltage modulation Adaptive Voltage Scaling / Dyn. Voltage Scaling Adaptive Voltage Scaling / Dyn. Voltage Scaling Power Gating Power Gating Scalable, fundamental solutions? Scalable, fundamental solutions? Most of these complicate the design/tool flow substantially…

October 2008 © 2008 AnaSIM 34 Addressing Scaling AND Power Planar device Scaling V T, V DD reaching limits V T, V DD reaching limits Loss of channel control Loss of channel control Variations (V T, L eff …) Variations (V T, L eff …) Leakage limiting gate dielectric scaling Leakage limiting gate dielectric scaling Double Gate devices Double Gate devices Lower leakage Lower leakage Lower parasitics (C, R) Lower parasitics (C, R) Lower fabrication cost Lower fabrication cost Lower delays  higher performance! Lower delays  higher performance! FinFET Source: L. Mathew, SOI 2007

October 2008 © 2008 AnaSIM 35 Planar Contender from Intel® Reference: Marczyk & Chau, Intel®, , 20 and 15nm transistors claimed… High-K integrated, provides low-leakage on-die CAP

October 2008 © 2008 AnaSIM 36 Double Gate Variants Gate 1 Gate 2 FINFETITFETMIGFET Source: L. Mathew, SOI 2007

October 2008 © 2008 AnaSIM 37 Lower Total Cost of DG Devices Substantially reduced Substantially reduced Processing steps Processing steps Leakage Leakage Improved Improved Parasitics/Performance Parasitics/Performance Record I ON /I OFF Record I ON /I OFF No area penalty / greater area utilization No area penalty / greater area utilization Novel circuits feasible Novel circuits feasible But challenges remain But challenges remain Process, Design Process, Design Source: L. Mathew, SOI 2007 “Very promising for low power, low cost Handheld applications”

October 2008 © 2008 AnaSIM 38 Summary Supply voltage minimization is key to IC energy management Supply voltage minimization is key to IC energy management Accurate, true-electromagnetic, spatio-temporal noise analysis essential Accurate, true-electromagnetic, spatio-temporal noise analysis essential Innovative power delivery and integrity management solutions are also needed Innovative power delivery and integrity management solutions are also needed CMOS Scaling has some distance to go with innovative devices CMOS Scaling has some distance to go with innovative devices 3-D (SiP, PoP, SAPI) integration will drive a more feasible continuation of Moore’s Law 3-D (SiP, PoP, SAPI) integration will drive a more feasible continuation of Moore’s Law

October 2008 © 2008 AnaSIM 39 Anasim Info Anasim bringing sea change into SoC methodology with physics-based analyses and high levels of abstraction Anasim bringing sea change into SoC methodology with physics-based analyses and high levels of abstraction Benefits to chip resource usage, area, energy, performance, and total design effort/cost Benefits to chip resource usage, area, energy, performance, and total design effort/cost Fills the GAP in Total Power Integrity analyses Fills the GAP in Total Power Integrity analyses Non-disruptive, Win-Win-Win engagement Non-disruptive, Win-Win-Win engagement Links, tel Links, tel. +1 Anasim White Papers pifp1.pdf, pifp2.pdf, pifp3.pdf Anasim White Papers pifp1.pdf, pifp2.pdf, pifp3.pdf Anasimpifp1.pdfpifp2.pdfpifp3.pdf Anasimpifp1.pdfpifp2.pdfpifp3.pdf Product -  -fp brochure Product -  -fp brochure  -fp brochure  -fp brochure ComLSI, parent co. ComLSI, parent co.parent coparent co

October 2008 © 2008 AnaSIM 40 Backup

October 2008 © 2008 AnaSIM 41 PI-FP Tool Environment Simulation netlist.TRAN 200e-12.PLOT 20.ACC PRINTNODE ALL Ggrid e-9 10e-9 Igrid pulse.txt 1 Ttline e-9 100e Ngrid pulse.txt : Current Source 0 22E E E E E E E E E E-12 0

October 2008 © 2008 AnaSIM 42 PI-FP Tool Environment contd. Multi-Grid design Multi-Grid design L calculation L calculation Planar or 3D Planar or 3D Include multiple chips in stacked or planar design Include multiple chips in stacked or planar design Code efficiency Code efficiency Each GRID on its own core (CPU) Each GRID on its own core (CPU)

October 2008 © 2008 AnaSIM 43 Floorplanning / Optimization GRID wire width, spacing, pitch GRID wire width, spacing, pitch Metal resource savings, routing / timing facilitation Metal resource savings, routing / timing facilitation DECAP optimization DECAP optimization Area savings Area savings Block placement tweaks for PI Block placement tweaks for PI Noise generation, propagation Noise generation, propagation Chip-Package co-simulation Chip-Package co-simulation Operating voltage (Energy) tuning Operating voltage (Energy) tuning Resonance detection and avoidance… Resonance detection and avoidance…

October 2008 © 2008 AnaSIM 44 IO Ring impact on Core Noise The voltage regulators, connecting between the IO Ring and the Core Grid are seen to become significant noise injection nodes with the inclusion of loads and the IO Ring. Pictures above are snapshots of dynamic plots. Analysis on a customer CLOCK chip