CSE331 W07&8.1Irwin Fall 2007 PSU CSE 331 Computer Organization and Design Fall 2007 Week 7&8 Section 1: Mary Jane Irwin ( Section 2: Krishna Narayanan Course material on ANGEL: cms.psu.edu [ adapted from D. Patterson slides ]

CSE331 W07&8.2Irwin Fall 2007 PSU Head’s Up  Last week’s material l Intro to VHDL  This week’s material l Number representation, basic arithmetic ops, MIPS ALU design -Reading assignment – PH , B.5-B.6  Next week’s material l Designing a MIPS single cycle datapath -Reading assignment – PH , B.7  Reminders l HW 6 is due Monday, Oct 29 th (by 11:55pm) l Quiz 5 closes Thursday, Oct 25 th (by 11:55pm) l Exam #1 take home solution due Thursday, Nov 1 st (by 11:55pm) l Exam #2 is Thursday, Nov 8, 6:30 to 7:45pm

CSE331 W07&8.3Irwin Fall 2007 PSU Architects write the checks that the design engineers have to cash. If the amount is too high, the whole project goes bankrupt. Design engineers must constantly juggle many conflicting demands: schedule, performance, power dissipation, features, testing, documentation, training and hiring. The Pentium Chronicles, Colwell, pg. 64 & 63

CSE331 W07&8.4Irwin Fall 2007 PSU Review: VHDL  Supports design, documentation, simulation & verification, and synthesis of hardware  Allows integrated design at behavioral and structural levels  Basic structure l Design entity-architecture descriptions l Time-based execution (discrete event simulation) model Design Entity-Architecture == Hardware Component Entity == External Characteristics Architecture (Body ) == Internal Behavior or Structure

CSE331 W07&8.5Irwin Fall 2007 PSU Review: Entity-Architecture Features  Entity defines externally visible characteristics l Ports: channels of communication -signal names for inputs, outputs, clocks, control l Generic parameters: define class of components -timing characteristics, size (fan-in), fan-out  Architecture defines the internal behavior or structure of the circuit l Declaration of internal signals l Description of behavior -collection of Concurrent Signal Assignment (CSA) statements (indicated by <=); can also model temporal behavior with the delay annotation -one or more processes containing CSAs and (sequential) variable assignment statements (indicated by :=) l Description of structure -interconnections of components; underlying behavioral models of each component must be specified

CSE331 W07&8.6Irwin Fall 2007 PSU Arithmetic  Where we've been l Abstractions -Instruction Set Architecture (ISA) -Assembly and machine language  What's up ahead l Implementing the architecture (in VHDL) 32 m (operation) result A B ALU 4 zeroovf 1 1

CSE331 W07&8.7Irwin Fall 2007 PSU ALU VHDL Representation entity ALU is port(A, B: in std_logic_vector (31 downto 0); m: in std_logic_vector (3 downto 0); result: out std_logic_vector (31 downto 0); zero: out std_logic; ovf: out std_logic) end entity ALU; architecture process_behavior of ALU is... begin ALU: process(A, B, m) begin... result := A + B;... end process ALU; end architecture process_behavior;

CSE331 W07&8.8Irwin Fall 2007 PSU Machine Number Representation  Bits are just bits (have no inherent meaning) l conventions define the relationships between bits and numbers  Binary numbers (base 2) - integers 0000  0001  0010  0011  0100  0101 ... l in decimal from 0 to 2 n -1 for n bits  Of course, it gets more complicated l storage locations (e.g., register file words) are finite, so have to worry about overflow (i.e., when the number is too big to fit into 32 bits) l have to be able to represent negative numbers, e.g., how do we specify -8 in addi$sp, $sp, -8#$sp = $sp - 8 l in real systems have to provide for more that just integers, e.g., fractions and real numbers (and floating point) and alphanumeric (characters)

CSE331 W07&8.9Irwin Fall 2007 PSU Possible Representations Sign Mag.Two’s Comp.One’s Comp = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +7  Issues: balance number of zeros ease of operations  Which one is best? Why?

CSE331 W07&8.10Irwin Fall 2007 PSU  32-bit signed numbers (2’s complement): two = 0 ten two = + 1 ten two = + 2 ten two = + 2,147,483,646 ten two = + 2,147,483,647 ten two = – 2,147,483,648 ten two = – 2,147,483,647 ten two = – 2,147,483,646 ten two = – 3 ten two = – 2 ten two = – 1 ten  What if the bit string represented addresses? l need operations that also deal with only positive (unsigned) integers maxint minint MIPS Representations

CSE331 W07&8.11Irwin Fall 2007 PSU  Negating a two's complement number – complement all the bits and then add a 1 l remember: “negate” and “invert” are quite different!  Converting n-bit numbers into numbers with more than n bits: l MIPS 16-bit immediate gets converted to 32 bits for arithmetic sign extend - copy the most significant bit (the sign bit) into the other bits > > sign extension versus zero extend ( lb vs. lbu ) Two's Complement Operations

CSE331 W07&8.12Irwin Fall 2007 PSU Design the MIPS Arithmetic Logic Unit (ALU)  Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu 32 m (operation) result A B ALU 4 zeroovf 1 1  With special handling for sign extend – addi, addiu, slti, sltiu zero extend – andi, ori, xori overflow detection – add, addi, sub

CSE331 W07&8.13Irwin Fall 2007 PSU MIPS Arithmetic and Logic Instructions R-type: I-Type: opRsRtRdfunct opRsRtImmed 16 Type opfunct ADDI001000xx ADDIU001001xx SLTI001010xx SLTIU001011xx ANDI001100xx ORI001101xx XORI001110xx LUI001111xx Type op funct ADD ADDU SUB SUBU AND OR XOR NOR Type opfunct SLT SLTU

CSE331 W07&8.14Irwin Fall 2007 PSU Design Trick: Divide & Conquer  Break the problem into simpler problems, solve them and glue together the solution  Example: assume the immediates have been taken care of before the ALU l now down to 10 operations l can encode in 4 bits 0add 1addu 2sub 3subu 4and 5or 6xor 7nor aslt bsltu

CSE331 W07&8.15Irwin Fall 2007 PSU  Just like in grade school (carry/borrow 1s)  Two's complement operations are easy do subtraction by negating and then adding 0111    Overflow (result too large for finite computer word) e.g., adding two n-bit numbers does not yield an n-bit number Addition & Subtraction

CSE331 W07&8.16Irwin Fall 2007 PSU  Just like in grade school (carry/borrow 1s)  Two's complement operations are easy l do subtraction by negating and then adding 0111    Overflow (result too large for finite computer word) e.g., adding two n-bit numbers does not yield an n-bit number Addition & Subtraction

CSE331 W07&8.17Irwin Fall 2007 PSU Building a 1-bit Binary Adder 1 bit Full Adder A B S carry_in carry_out S = A xor B xor carry_in carry_out = A&B | A&carry_in | B&carry_in (majority function)  How can we use it to build a 32-bit adder?  How can we modify it easily to build an adder/subtractor? AB carry_incarry_out S

CSE331 W07&8.18Irwin Fall 2007 PSU Building 32-bit Adder 1-bit FA A0A0 B0B0 S0S0 c 0 =carry_in c1c1 1-bit FA A1A1 B1B1 S1S1 c2c2 A2A2 B2B2 S2S2 c3c3 c 32 =carry_out 1-bit FA A 31 B 31 S 31 c  Just connect the carry-out of the least significant bit FA to the carry-in of the next least significant bit and connect...  Ripple Carry Adder (RCA) advantage: simple logic, so small (low cost) disadvantage: slow and lots of glitching (so lots of energy consumption)

CSE331 W07&8.19Irwin Fall 2007 PSU A 32-bit Ripple Carry Adder/Subtractor  Remember 2’s complement is just complement all the bits add a 1 in the least significant bit A 0111  0111 B  + 1-bit FA S0S0 c 0 =carry_in c1c1 1-bit FA S1S1 c2c2 S2S2 c3c3 c 32 =carry_out 1-bit FA S 31 c A0A0 A1A1 A2A2 A 31 B0B0 B1B1 B2B2 B 31 add/sub B0B0 control (0=add,1=sub) B 0 if control = 0, !B 0 if control = 1

CSE331 W07&8.20Irwin Fall 2007 PSU A 32-bit Ripple Carry Adder/Subtractor  Remember 2’s complement is just complement all the bits add a 1 in the least significant bit A 0111  0111 B  + 1-bit FA S0S0 c 0 =carry_in c1c1 1-bit FA S1S1 c2c2 S2S2 c3c3 c 32 =carry_out 1-bit FA S 31 c A0A0 A1A1 A2A2 A 31 B0B0 B1B1 B2B2 B 31 add/sub B0B0 control (0=add,1=sub) B 0 if control = 0 !B 0 if control =

CSE331 W07&8.21Irwin Fall 2007 PSU Overflow Detection and Effects  Overflow: the result is too large to represent in the number of bits allocated  When adding operands with different signs, overflow cannot occur! Overflow occurs when l adding two positives yields a negative l or, adding two negatives gives a positive l or, subtract a negative from a positive gives a negative l or, subtract a positive from a negative gives a positive  On overflow, an exception (interrupt) occurs l Control jumps to predefined address for exception l Interrupted address (address of instruction causing the overflow) is saved for possible resumption  Don't always want to detect (interrupt on) overflow

CSE331 W07&8.22Irwin Fall 2007 PSU New MIPS Instructions CategoryInstrOp CodeExampleMeaning Arithmetic (R & I format) add unsigned0 and 21addu $s1, $s2, $s3$s1 = $s2 + $s3 sub unsigned0 and 23subu $s1, $s2, $s3$s1 = $s2 - $s3 add imm.unsigned 9addiu $s1, $s2, 6$s1 = $s2 + 6 Data Transfer ld byte unsigned 24lbu $s1, 25($s2)$s1 = Mem($s2+25) ld half unsigned25lhu $s1, 25($s2)$s1 = Mem($s2+25) Cond. Branch (I & R format) set on less than unsigned 0 and 2bsltu $s1, $s2, $s3if ($s2<$s3) $s1=1 else $s1=0 set on less than imm unsigned bsltiu $s1, $s2, 6if ($s2<6) $s1=1 else $s1=0  Sign extend – addiu, addiu, slti, sltiu  Zero extend – andi, ori, xori  Overflow detected – add, addi, sub

CSE331 W07&8.23Irwin Fall 2007 PSU End of First Lecture of the Week

CSE331 W07&8.24Irwin Fall 2007 PSU Those who are not engineers know two certainties: death and taxes. Engineers know a third: there are no perfect designs. … The FDIV flaw was a subtle, complex bug that survived both design and validation. The Pentium Chronicles, Colwell

CSE331 W07&8.25Irwin Fall 2007 PSU Review: MIPS Arithmetic Instructions R-type: I-Type: opRsRtRdfunct opRsRtImmed 16 Typeop funct ADD ADDU SUB SUBU AND OR XOR NOR Typeop funct SLT SLTU add 1addu 2sub 3subu 4and 5or 6xor 7nor aslt bsltu l expand immediates to 32 bits before ALU l 10 operations so can encode in 4 bits 32 m (operation) result A B ALU 4 zeroovf 1 1

CSE331 W07&8.26Irwin Fall 2007 PSU Review: A 32-bit Adder/Subtractor 1-bit FA S0S0 c 0 =carry_in c1c1 1-bit FA S1S1 c2c2 S2S2 c3c3 c 32 =carry_out 1-bit FA S 31 c  Built out of 32 full adders (FAs) A0A0 B0B0 A1A1 B1B1 A2A2 B2B2 A 31 B 31 add/subt 1 bit FA A B S carry_in carry_out S = A xor B xor carry_in carry_out = A&B | A&carry_in | B&carry_in (majority function)  Small but slow!

CSE331 W07&8.27Irwin Fall 2007 PSU Minimal Implementation of a Full Adder architecture concurrent_behavior of full_adder is signal t1, t2, t3, t4, t5: std_logic; begin t1 <= not A after 1 ns; t2 <= not cin after 1 ns; t4 <= not((A or cin) and B) after 2 ns; t3 <= not((t1 or t2) and (A or cin)) after 2 ns; t5 <= t3 nand B after 2 ns; S <= not((B or t3) and t5) after 2 ns; cout <= not(t1 or t2) and t4) after 2 ns; end architecture concurrent_behavior;  Can you create the equivalent schematic? Can you determine worst case delay (the worst case timing path through the circuit)?  Gate library: inverters, 2-input nands, or-and-inverters

CSE331 W07&8.28Irwin Fall 2007 PSU  Also need to support the logic operations ( and, nor, or, xor ) l Bit wise operations (no carry operation involved) l Need a logic gate for each function and a mux to choose the output  Also need to support the set-on-less-than instruction ( slt ) l Uses subtraction to determine if (a – b) < 0 (implies a < b)  Also need to support test for equality ( bne, beq ) l Again use subtraction: (a - b) = 0 implies a = b  Also need to add overflow detection hardware overflow detection enabled only for add, addi, sub  Immediates are sign extended outside the ALU with wiring (i.e., no logic needed) Tailoring the ALU to the MIPS ISA

CSE331 W07&8.29Irwin Fall 2007 PSU A Simple ALU Cell with Logic Op Support 1-bit FA carry_in carry_out A B add/subt result op

CSE331 W07&8.30Irwin Fall 2007 PSU An Alternative ALU Cell 1-bit FA carry_in s1 s2 s0 result carry_out A B

CSE331 W07&8.31Irwin Fall 2007 PSU The Alternative ALU Cell’s Control Codes s2s1s0c_inresultfunction 0000Atransfer A 0001A + 1increment A 0010A + Badd 0011A + B + 1add with carry 0100A – B – 1subt with borrow 0101A – Bsubtract 0110A – 1decrement A 0111Atransfer A 100xA or Bor 101xA xor Bxor 110xA and Band 111x!Acomplement A

CSE331 W07&8.32Irwin Fall 2007 PSU Modifying the ALU Cell for slt 1-bit FA A B result carry_in carry_out add/subtop add/subt less

CSE331 W07&8.33Irwin Fall 2007 PSU Modifying the ALU for slt + A1A1 B1B1 result 1 less + A0A0 B0B0 result 0 less + A 31 B 31 result 31 less...  First perform a subtraction  Make the result 1 if the subtraction yields a negative result  Make the result 0 if the subtraction yields a positive result

CSE331 W07&8.34Irwin Fall 2007 PSU Modifying the ALU for slt 0 0 set  First perform a subtraction  Make the result 1 if the subtraction yields a negative result  Make the result 0 if the subtraction yields a positive result tie the most significant sum bit (sign bit) to the low order less input

CSE331 W07&8.35Irwin Fall 2007 PSU Modifying the ALU for Zero + A1A1 B1B1 result 1 less + A0A0 B0B0 result 0 less + A 31 B 31 result 31 less set  First perform subtraction  Insert additional logic to detect when all result bits are zero add/subt op

CSE331 W07&8.36Irwin Fall 2007 PSU Modifying the ALU for Zero + A1A1 B1B1 result 1 less + A0A0 B0B0 result 0 less + A 31 B 31 result 31 less set  First perform subtraction  Insert additional logic to detect when all result bits are zero zero... add/subt op Note zero is a 1 when result is all zeros

CSE331 W07&8.37Irwin Fall 2007 PSU Overflow Detection  Overflow occurs when the result is too large to represent in the number of bits allocated l adding two positives yields a negative l or, adding two negatives gives a positive l or, subtract a negative from a positive gives a negative l or, subtract a positive from a negative gives a positive  On your own: Prove you can detect overflow by: l Carry into MSB xor Carry out of MSB –4 – 5

CSE331 W07&8.38Irwin Fall 2007 PSU Overflow Detection  Overflow occurs when the result is too large to represent in the number of bits allocated l adding two positives yields a negative l or, adding two negatives gives a positive l or, subtract a negative from a positive gives a negative l or, subtract a positive from a negative gives a positive  On your own: Prove you can detect overflow by: l Carry into MSB xor Carry out of MSB – –4 –

CSE331 W07&8.39Irwin Fall 2007 PSU Modifying the ALU for Overflow + A1A1 B1B1 result 1 less + A0A0 B0B0 result 0 less + A 31 B 31 result 31 less set  Modify the most significant cell to determine overflow output setting  Enable overflow bit setting for signed arithmetic ( add, addi, sub ) zero... add/subt op overflow

CSE331 W07&8.40Irwin Fall 2007 PSU But What about Performance?  Critical path of n-bit ripple-carry adder is n*CP  Design trick – throw hardware at it (Carry Lookahead) A0 B0 1-bit ALU Result0 CarryIn0 CarryOut0 A1 B1 1-bit ALU Result1 CarryIn1 CarryOut1 A2 B2 1-bit ALU Result2 CarryIn2 CarryOut2 A3 B3 1-bit ALU Result3 CarryIn3 CarryOut3

CSE331 W07&8.41Irwin Fall 2007 PSU  More complicated than addition l Can be accomplished via shifting and adding 0010 (multiplicand) x_1011 (multiplier) (partial product 0000 array) (product)  Double precision product produced  More time and more area to compute Multiplication

CSE331 W07&8.42Irwin Fall 2007 PSU  Multiply produces a double precision product mult $s0, $s1 # hi||lo = $s0 * $s1 Low-order word of the product is left in processor register lo and the high-order word is left in register hi Instructions mfhi rd and mflo rd are provided to move the product to (user accessible) registers in the register file MIPS Multiply Instruction op rs rt rd shamt funct  Multiplies are done by fast, dedicated hardware and are much more complex (and slower) than adders  Hardware dividers are even more complex and even slower; ditto for hardware square root

CSE331 W07&8.43Irwin Fall 2007 PSU Division  Division is just a bunch of quotient digit guesses and left shifts and subtracts dividend divisor partial remainder array quotient n n remainder n

CSE331 W07&8.44Irwin Fall 2007 PSU  Divide generates the reminder in hi and the quotient in lo div $s0, $s1 # lo = $s0 / $s1 # hi = $s0 mod $s1 Instructions mflo rd and mfhi rd are provided to move the quotient and reminder to (user accessible) registers in the register file MIPS Divide Instruction  As with multiply, divide ignores overflow so software must determine if the quotient is too large. Software must also check the divisor to avoid division by 0. op rs rt rd shamt funct

CSE331 W07&8.45Irwin Fall 2007 PSU Shift Operations  Shifts move all the bits in a word left or right sll $t2, $s0, 8 #$t2 = $s0 << 8 bits srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits op rs rt rd shamt funct  Notice that a 5-bit shamt field is enough to shift a 32-bit value 2 5 – 1 or 31 bit positions  Logical shifts fill with zeros, arithmetic left shifts fill with the sign bit  The shift operation is implemented by hardware separate from the ALU l using a barrel shifter (which would takes lots of gates in discrete logic, but is pretty easy to implement in VLSI)

CSE331 W07&8.46Irwin Fall 2007 PSU Parallel Programmable Shifters Data In Control Data Out Shift amount (Sh 4 Sh 3 Sh 2 Sh 1 Sh 0 ) Shift direction (left, right) Shift type (logical, arithmetic) =

CSE331 W07&8.47Irwin Fall 2007 PSU Logarithmic Shifter Structure Data In Data Out shifts of 0 or 1 bits !Sh 0 Sh 0 0,1 shifts shifts of 0 or 2 bits !Sh 1 Sh 1 0,1,2,3 shifts shifts of 0 or 4 bits !Sh 2 Sh 2 0,1,2,3,4, 5,6,7 shifts shifts of 0 or 8 bits !Sh 3 Sh 3 0,1,2…15 shifts shifts of 0 or 16 bits !Sh 4 Sh 4 0,1,2…31 shifts

CSE331 W07&8.48Irwin Fall 2007 PSU Logarithmic Shifter Structure Data In Data Out shifts of 0 or 1 bits !Sh 0 Sh 0 0,1 shifts shifts of 0 or 2 bits !Sh 1 Sh 1 0,1,2,3 shifts shifts of 0 or 4 bits !Sh 2 Sh 2 0,1,2,3,4, 5,6,7 shifts shifts of 0 or 8 bits !Sh 3 Sh 3 0,1,2…15 shifts shifts of 0 or 16 bits !Sh 4 Sh 4 0,1,2…31 shifts Sh 0 & right datain i dataout i datain i-1 datain i+1 Sh 0 & left !Sh 0 Sh 1 & right datain i dataout i datain i-2 datain i+2 Sh 1 & left !Sh 1

CSE331 W07&8.49Irwin Fall 2007 PSU Wrap-Up  We can build an ALU to support the MIPS ISA l we can efficiently perform subtraction using two’s complement l we can replicate a 1-bit ALU to produce a 32-bit ALU  Important points about hardware l all of the gates are always working (concurrently) l the speed of a gate is affected by the number of inputs to the gate (fan-in) and the number of gates that the output is connected to (fan-out) l the speed of a circuit is affected by the speed of and number of gates in series (on the “critical path” or the “number of levels of logic”) and the length of wires interconnecting the gates  Our primary focus is comprehension, however l clever changes to organization can improve performance (similar to using better algorithms in software)