FET ( Field Effect Transistor) Few important advantages of FET over conventional Transistors Unipolar device i. e. operation depends on only one type of charge carriers (h or e) Voltage controlled Device (gate voltage controls drain current) Very high input impedance (109-1012 ) Source and drain are interchangeable in most Low-frequency applications Low Voltage Low Current Operation is possible (Low-power consumption) Less Noisy as Compared to BJT No minority carrier storage (Turn off is faster) Self limiting device Very small in size, occupies very small space in ICs Low voltage low current operation is possible in MOSFETS Zero temperature drift of output is possible FET’s are also generally more static sensitive than BJT’s.

Types of Field Effect Transistors (The Classification) JFET MOSFET (IGFET) n-Channel JFET p-Channel JFET FET Enhancement MOSFET Depletion MOSFET n-Channel EMOSFET n-Channel DMOSFET p-Channel DMOSFET p-Channel EMOSFET

The Junction Field Effect Transistor (JFET) Figure: n-Channel JFET.

SYMBOLS Gate Drain Source Gate Drain Source Gate Drain Source n-channel JFET Offset-gate symbol n-channel JFET p-channel JFET

Figure: n-Channel JFET and Biasing Circuit. Biasing the JFET Figure: n-Channel JFET and Biasing Circuit.

Construction and characteristics of JFET JFET operation can be compared to a water faucet: The source of water pressure – accumulated electrons at the negative pole of the applied voltage from Drain to Source The drain of water – electron deficiency (or holes) at the positive pole of the applied voltage from Drain to Source. The control of flow of water – Gate voltage that controls the width of the n-channel, which in turn controls the flow of electrons in the n-channel from source to drain.

Construction and characteristics of JFET N-Channel JFET Circuit Layout

JFET Operating Characteristics There are three basic operating conditions for a JFET: VGS = 0, VDS increasing to some positive value B. VGS < 0, VDS at some positive value C. Voltage-Controlled Resistor

VGS = 0, VDS increasing to some positive value Three things happen when VGS = 0 and VDS is increased from 0 to a more positive voltage: • the depletion region between p-gate and n-channel increases as electrons from n-channel combine with holes from p-gate. increasing the depletion region, decreases the size of the n-channel which increases the resistance of the n-channel. But even though the n-channel resistance is increasing, the current (ID) from Source to Drain through the n-channel is increasing. This is because VDS is increasing.

VGS = 0, VDS increasing to some positive value The flow of charge is relatively uninhibited and limited solely by the resistance of the n-channel between drain and source. The depletion region is wider near the top of both p-type materials. ID will establish the voltage level through the channel. The result: upper region of the p-type material will be reversed biased by about 1.5V with the lower region only reversed biased by 0.5V (greater applied reverse bias, the wider depletion region).

VGS = 0, VDS increasing to some positive value IG=0A  p-n junction is reverse-biased for the length of the channel results in a gate current of zero amperes. As the VDS is increased from 0 to a few volts, the current will increase as determined by Ohm’s Law. VDS increase and approaches a level referred to as Vp, the depletion region will widen, causing reduction in the channel width. (p large, n small). Reduced part of conduction causes the resistance to increase. If VDS is increased to a level where it appears that the 2 depletion regions would touch (pinch-off)

VGS = 0, VDS increasing to some positive value Vp = pinch off voltage. ID maintain the saturation level defined as IDSS Once the VDS > VP, the JFET has the characteristics of a current source. As shown in figure, the current is fixed at ID = IDSS, the voltage VDS (for level >Vp) is determined by the applied load. IDSS is derived from the fact that it is the drain-to-source current with short circuit connection from gate to source. IDSS is the max drain current for a JFET and is defined by the conditions VGS=0V and VDS > | Vp|.

VGS = 0, VDS increasing to some positive value At the pinch-off point: any further increase in VGS does not produce any increase in ID. VGS at pinch-off is denoted as Vp. • ID is at saturation or maximum. It is referred to as IDSS. • The ohmic value of the channel is at maximum.

Typical JFET operation

JFET modeling when ID=IDSS, VGS=0, VDS>VP

VGS < 0, VDS at some positive value VGS is the controlling voltage of the JFET. For n-channel devices, the controlling voltage VGS is made more and more negative from its VGS = 0V level. The effect of the applied negative VGS is to establish depletion regions similar to those obtained with VGS=0V but a lower level of VDS  to reach the saturation level at a lower level of VDS.

VGS < 0, VDS at some positive value When VGS = -Vp will be sufficiently negative to establish saturation level that is essentially 0mA, the device has been ‘turn off’. The level of the VGS that results in ID = 0 mA is defined by VGS = Vp, with Vp being a negative voltage for n-channel devices and a positive voltage or p-channel JFETs. In this region, JFET can actually be employed as a variable resistor whose resistance is controlled by the applied gate to source voltage. A VGS becomes more and more negative; the slope of each curve becomes more and more horizontal.

VGS < 0, VDS at some positive value The region to the right of the pinch-off locus of the figure is the region typically employed in linear amplifiers (amplifiers with min distortion of the applied signal) and is commonly referred to as the constant-current, saturation, or linear amplification region.

Characteristic curves for N-channel JFET

Voltage-Controlled Resistor The region to the left of the pinch-off point is called the ohmic region. The JFET can be used as a variable resistor, where VGS controls the drain-source resistance (rd). As VGS becomes more negative, the resistance (rd) increases.

And as summary in practical…

(Note: The two gate regions of each FET are connected to each other.) Operation of JFET at Various Gate Bias Potentials Figure: The nonconductive depletion region becomes broader with increased reverse bias. (Note: The two gate regions of each FET are connected to each other.)

Operation of a JFET Drain - N Gate P P + + - DC Voltage Source - N +

Output or Drain (VD-ID) Characteristics of n-JFET Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics. Non-saturation (Ohmic) Region: The drain current is given by Saturation (or Pinchoff) Region: Where, IDSS is the short circuit drain current, VP is the pinch off voltage

Figure: n-Channel FET for vGS = 0. Simple Operation and Break down of n-Channel JFET Figure: n-Channel FET for vGS = 0.

N-Channel JFET Characteristics and Breakdown Break Down Region Figure: If vDG exceeds the breakdown voltage VB, drain current increases rapidly.

VD-ID Characteristics of EMOS FET Locus of pts where Saturation or Pinch off Reg. Figure: Typical drain characteristics of an n-channel JFET.

Figure: Transfer (or Mutual) Characteristics of n-Channel JFET Transfer (Mutual) Characteristics of n-Channel JFET IDSS VGS (off)=VP Figure: Transfer (or Mutual) Characteristics of n-Channel JFET

JFET Transfer Curve This graph shows the value of ID for a given value of VGS

Biasing Circuits used for JFET Fixed bias circuit Self bias circuit Potential Divider bias circuit

JFET (n-channel) Biasing Circuits For Fixed Bias Circuit Applying KVL to gate circuit we get and Where, Vp=VGS-off & IDSS is Short ckt. IDS For Self Bias Circuit

JFET Biasing Circuits Count… or Fixed Bias Ckt.

JFET Self (or Source) Bias Circuit This quadratic equation can be solved for VGS & IDS

The Potential (Voltage) Divider Bias