Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation regions of cutoff, triode and saturation. Develop mathematical models for i-v characteristics of MOSFETs. Introduce graphical representations for output and transfer characteristic descriptions of electron devices. Define and contrast characteristics of enhancement-mode and depletion-mode FETs. Define symbols to represent FETs in circuit schematics. Investigate circuits that bias transistors into different operating regions. Learn basic structure and mask layout for MOS transistors and circuits. Explore MOS device scaling Contrast 3 and 4 terminal device behavior. Describe sources of capacitance in MOSFETs. Explore FET modeling in SPICE. Microelectronic Circuit Design, 4E McGraw-Hill

4.1 MOS Capacitor Structure First electrode- Gate: Consists of low-resistivity material such as metal or polycrystalline silicon Second electrode- Substrate or Body: n- or p-type semiconductor Dielectric- Silicon dioxide: stable high-quality electrical insulator between gate and substrate. Microelectronic Circuit Design, 4E McGraw-Hill

Substrate Conditions for Different Biases Accumulation Depletion Accumulation VG << VTN Depletion VG < VTN Inversion VG > VTN Inversion Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill Low-frequency C-V Characteristics for MOS Capacitor on P-type Substrate MOS capacitance is non-linear function of voltage. Total capacitance in any region dictated by the separation between capacitor plates. Total capacitance modeled as series combination of fixed oxide capacitance and voltage-dependent depletion layer capacitance. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill Capacitors in series Capacitor C1 in series with Capacitor C2 Q1 = C1 * V1 Q2 = C2 * V2 Totally Q = Ceq * V = Q1= Q2, V = V1 + V2 Ceq = Q/V = Q/(V1 + V2) = Q/(Q1/C1 +Q2/C2) = 1/(1/C1 + 1/C2) = C1*C2/(C1 + C2) Microelectronic Circuit Design, 4E McGraw-Hill

4.2 NMOS Transistor: Structure 4 device terminals: Gate(G), Drain(D), Source(S) and Body(B). Source and drain regions form pn junctions with substrate. vSB, vDS and vGS always positive during normal operation. vSB always < vDS and vGS to reverse bias pn junctions Microelectronic Circuit Design, 4E McGraw-Hill

NMOS Transistor: Qualitative I-V Behavior VGS <<VTN : Only small leakage current flows. VGS <VTN: Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. VGS >VTN: Channel formed between source and drain. If vDS > 0,, finite iD flows from drain to source. iB=0 and iG=0. Microelectronic Circuit Design, 4E McGraw-Hill

NMOS Transistor: Triode Region Characteristics for where, Kn= Kn’ W/L Kn’=mnCox’’ (A/V2) Cox’’=ox / Tox  ox= oxide permittivity (F/cm) Tox= oxide thickness (cm) Microelectronic Circuit Design, 4E McGraw-Hill

NMOS Transistor: Triode Region Characteristics (contd.) Output characteristics appear to be linear. FET behaves like a gate-source voltage-controlled resistor between source and drain with Microelectronic Circuit Design, 4E McGraw-Hill

MOSFET as Voltage-Controlled Resistor Example 1: Voltage-Controlled Attenuator If Kn= 500mA/V2, VTN =1V, R = 2k and VGG =1.5V, then, To maintain triode region operation, or or Microelectronic Circuit Design, 4E McGraw-Hill

NMOS Transistor: Saturation Region If vDS increases above triode region limit, channel region disappears, also said to be pinched-off. Current saturates at constant value, independent of vDS. Saturation region operation mostly used for analog amplification. Microelectronic Circuit Design, 4E McGraw-Hill

NMOS Transistor: Saturation Region (contd.) for is also called saturation or pinch-off voltage Microelectronic Circuit Design, 4E McGraw-Hill

Transconductance of a MOS Device Transconductance relates the change in drain current to a change in gate-source voltage Taking the derivative of the expression for the drain current in saturation region, Microelectronic Circuit Design, 4E McGraw-Hill

Channel-Length Modulation As vDS increases above vDSAT, length of depleted channel beyond pinch-off point, DL, increases and actual L decreases. iD increases slightly with vDS instead of being constant. l = channel length modulation parameter Microelectronic Circuit Design, 4E McGraw-Hill

Depletion-Mode MOSFETS NMOS transistors with Ion implantation process used to form a built-in n-type channel in device to connect source and drain by a resistive channel Non-zero drain current for vGS = 0, negative vGS required to turn device off. Microelectronic Circuit Design, 4E McGraw-Hill

Transfer Characteristics of MOSFETS Plots drain current versus gate-source voltage for a fixed drain-source voltage Microelectronic Circuit Design, 4E McGraw-Hill

Body Effect or Substrate Sensitivity Non-zero vSB changes threshold voltage, causing substrate sensitivity modeled by where VTO= zero substrate bias for VTN (V) g= body-effect parameter ( ) 2FF= surface potential parameter (V) Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill NMOS Model Summary Microelectronic Circuit Design, 4E McGraw-Hill

4.3 Enhancement-Mode PMOS Transistors: Structure (11/14) P-type source and drain regions in n-type substrate. vGS < 0 required to create p-type inversion layer in channel region For current flow, vGS < vTP To maintain reverse bias on source-substrate and drain-substrate junctions, vSB < 0 and vDB < 0 Positive bulk-source potential causes VTP to become more negative Microelectronic Circuit Design, 4E McGraw-Hill

Enhancement-Mode PMOS Transistors: Output Characteristics For , transistor is off. For more negative vGS, drain current increases in magnitude. PMOS is in triode region for small values of VDS and in saturation for larger values. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill PMOS Model Summary Microelectronic Circuit Design, 4E McGraw-Hill

4.4 MOSFET Circuit Symbols (g) and (i) are the most commonly used symbols in VLSI logic design. MOS devices are symmetric. In NMOS, n+ region at higher voltage is the drain. In PMOS p+ region at lower voltage is the drain Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill

4.5 Internal Capacitances in Electronic Devices Limit high-frequency performance of the electronic device they are associated with. Limit switching speed of circuits in logic applications Limit frequency at which useful amplification can be obtained in amplifiers. MOSFET capacitances depend on operation region and are non-linear functions of voltages at device terminals. Microelectronic Circuit Design, 4E McGraw-Hill

NMOS Transistor Capacitances: Triode Region Cox” = Gate-channel capacitance per unit area (F/m2). CGC = Total gate channel capacitance. CGS = Gate-source capacitance. CGD = Gate-drain capacitance. CGSO and CGDO = overlap capacitances (F/m). Microelectronic Circuit Design, 4E McGraw-Hill

NMOS Transistor Capacitances: Triode Region (contd.) CSB = Source-bulk capacitance. CDB = Drain-bulk capacitance. AS and AD = Junction bottom area capacitance of the source and drain regions. PS and PD = Perimeter of the source and drain junction regions. Microelectronic Circuit Design, 4E McGraw-Hill

NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel Microelectronic Circuit Design, 4E McGraw-Hill

NMOS Transistor Capacitances: Cutoff Region Conducting channel region completely gone. CGB = Gate-bulk capacitance CGBO = gate-bulk capacitance per unit width. Microelectronic Circuit Design, 4E McGraw-Hill

SPICE Model for NMOS Transistor Typical default values used by SPICE: Kn or Kp = 20 mA/V2 g = 0 l = 0 VTO = 1 V mn or mp = 600 cm2/V.s 2FF = 0.6 V CGDO = CGSO = CGBO = CJSW = 0 Tox= 100 nm Microelectronic Circuit Design, 4E McGraw-Hill

MOS Transistor Scaling Drain current: Gate Capacitance: where t is the circuit delay in a logic circuit. Microelectronic Circuit Design, 4E McGraw-Hill

MOS Transistor Scaling (contd.) Circuit and Power Densities: Power-Delay Product: Cutoff Frequency: fT improves with square of channel length reduction Microelectronic Circuit Design, 4E McGraw-Hill

MOS Transistor Scaling (contd.) High Field Limitations: High electric fields arise if technology is scaled down with supply voltage constant. Cause reduction in mobility of MOS transistor, breakdown of linear relationship between mobility and electric field and carrier velocity saturation. Ultimately results in reduced long-term reliability and breakdown of gate oxide or pn junction. Drain current in saturation region is linearised to where, vSAT is carrier saturation velocity Microelectronic Circuit Design, 4E McGraw-Hill

MOS Transistor Scaling (contd.) Sub-threshold Conduction: ID decreases exponentially for VGS<VTN. Reciprocal of the slope in mV/decade gives the turn off rate for the MOSFET. VTN should be reduced if dimensions are scaled down, but curve in sub-threshold region shifts horizontally instead of scaling with VTN. Microelectronic Circuit Design, 4E McGraw-Hill

Process-defining Factors Minimum Feature Size, F : Width of smallest line or space that can be reliably transferred to wafer surface using given generation of lithographic manufacturing tools Alignment Tolerance, T: Maximum misalignment that can occur between two mask levels during fabrication Microelectronic Circuit Design, 4E McGraw-Hill

Mask Sequence for a Polysilicon-Gate Transistor Mask 1: Defines active area or thin oxide region of transistor Mask 2: Defines polysilicon gate of transistor, aligns to mask 1 Mask 3: Delineates the contact window, aligns to mask 2. Mask 4: Delineates the metal pattern, aligns to mask 3. Channel region of transistor formed by intersection of first two mask layers. Source and Drain regions formed wherever mask 1 is not covered by mask 2 Microelectronic Circuit Design, 4E McGraw-Hill

Basic Ground Rules for Layout F=2 L T=F/2=L, L could be 1, 0.5, 0.25 mm, etc. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill MOSFET Biasing ‘Bias’ sets the DC operating point around which the device operates. The ‘signal’ is actually comprised of relatively small changes in the DC current and/or voltage bias. Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis Approach Assume an operation region (generally the saturation region) Use circuit analysis to find VGS Use VGS to calculate ID, and ID to find VDS Check validity of operation region assumptions Change assumptions and analyze again if required. NOTE : An enhancement-mode device with VDS = VGS is always in saturation Microelectronic Circuit Design, 4E McGraw-Hill

Four-Resistor and Two-Resistor Biasing Provide excellent bias for transistors in discrete circuits. Stabilize bias point with respect to device parameter and temperature variations using negative feedback. Use single voltage source to supply both gate-bias voltage and drain current. Generally used to bias transistors in saturation region. Two-resistor biasing uses lesser components that four-resistor biasing and also isolates drain and gate terminals Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 1 (Constant Gate-Source Voltage Biasing) Problem: Find Q-pt (ID, VDS , VGS) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Assumption: Transistor is saturated, IG=IB=0 Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS and then use this to find ID. With ID, we can then calculate VDS. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill Bias Analysis: Example 1 (Constant Gate-Source Voltage Biasing)(contd.) Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (50.0 mA, 5.00 V) with VGS= 3.00 V Discussion: The Q-point of this circuit is quite sensitive to changes in transistor characteristics, so it is not widely used. Since IG=0, Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 2 (Load Line Analysis) Problem: Find Q-pt (ID, VDS , VGS) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumption: Transistor is saturated, IG=IB=0 Analysis: For circuit values above, load line becomes Use this to find two points on the load line. Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 2 (Load Line Analysis)(contd.) @VDS=0, ID=100uA @ID=0, VDS=10V Plotting on device characteristic yields Q-pt at intersection with VGS = 3V device curve. Check: The load line approach agrees with previous calculation. Q-pt: (50.0 mA, 5.00 V) with VGS= 3.00 V Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation) Assumption: Transistor is saturated, IG=IB=0 Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS and then use this to find ID. With ID, we can then calculate VDS. Problem: Find Q-pt (ID, VDS , VGS) of previous example, given =0.02 V-1. Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation) Check: VDS >VGS -VTN. Hence saturation region assumption is correct. Q-pt: (54.5 mA, 4.55 V) with VGS = 3.00 V Discussion: The bias levels have changed by about 10%. Typically, component values will vary more than this, so there is little value in including  effects in most circuits. Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 4 (Four-Resistor Biasing) Assumption: Transistor is saturated, IG = IB = 0 Analysis: First, simplify circuit, split VDD into two equal-valued sources and apply Thevenin transformation to find VEQ and REQ for gate-bias voltage Problem: Find Q-pt (ID, VDS) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 4 (Four-Resistor Biasing) Since VGS<VTN for VGS= -2.71 V and MOSFET will be cut-off, and ID= 34.4 mA Also, Since IG = 0, VDS > VGS - VTN. Hence saturation region assumption is correct. Q-pt: (34.4 mA, 6.08 V) with VGS = 2.66 V Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 5 (Four-Resistor Biasing with Body Effect) Analysis with body effect using same assumptions as in example 1: Iterative solution can be found by following steps: Estimate value of ID and use it to find VGS and VSB Use VSB to calculate VTN Find ID’ using above 2 steps If ID’ is not same as original ID estimate, start again. Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 5 (Four-Resistor Biasing) (contd.) The iteration sequence leads to ID= 88.0 mA, VTN = 1.41 V, VDS >VGS - VTN. Hence saturation region assumption is correct. Q-pt: (88.0 mA, 6.48 V) Check: VDS > VGS - VTN, therefore still in active region. Discussion: Body effect has decreased current by 12% and increased threshold voltage by 40%. Microelectronic Circuit Design, 4E McGraw-Hill

What if Veq = +4 V +- 1 Volt, Vds = ? An amplifier? Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 6 (Two-Resistor Feedback Biasing) Since VGS <VTN for VGS = -0.769 V and MOSFET will be cut-off, Assumption: IG = IB = 0, transistor is saturated (since VDS= VGS) Analysis: and ID= 130 mA VDS >VGS - VTN. Hence saturation region assumption is correct. Q-pt: (130 mA, 2.00 V) Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 7 ( Biasing in Triode Region) Also But VDS <VGS - VTN. Hence, saturation region assumption is incorrect. Using triode region equation, Assumption: IG = IB = 0, transistor is saturated (since VDS = VGS) Analysis: VGS =VDD=4 V and ID=1.06 mA VDS < VGS - VTN, transistor is in triode region Q-pt: (1.06 mA, 2.3 V) Microelectronic Circuit Design, 4E McGraw-Hill

Bias Analysis: Example 8 (Two-Resistor biasing for PMOS Transistor) Also Since VGS= -0.369 V is less than VTP= -2 V, VGS = -3.45 V ID = 52.5 mA and VGS = -3.45 V Assumption: IG = IB = 0, transistor is saturated (since VDS= VGS) Analysis: Hence saturation assumption is correct. Q-pt: (52.5 mA, -3.45 V) Microelectronic Circuit Design, 4E McGraw-Hill

Junction Field-Effect Transistor (JFET) Structure Much lower input current and much higher input impedance than the BJT. In triode region, JFET is a voltage-controlled resistor, r = resistivity of channel L = channel length W = channel width between pn junction depletion regions t = channel depth Inherently a depletion-mode device n-type semiconductor block houses the channel region in n-channel JFET. Two pn junctions form the gate. Current enters channel at the drain and exits at source. Microelectronic Circuit Design, 4E McGraw-Hill

JFET with Gate-Source Bias vGS = 0, gate isolated from channel. VP < vGS < 0, W’ < W, and channel resistance increases; gate-source junction is reverse-biased, iG almost 0. vGS = VP < 0, channel region pinched-off, channel resistance is infinite. Microelectronic Circuit Design, 4E McGraw-Hill

JFET Channel with Drain-Source Bias With constant vGS, depletion region near drain increases with vDS. At vDSP = vGS - VP , channel is totally pinched-off; iD is saturated. JFET also suffers from channel-length modulation like MOSFET at larger values of vDS. Microelectronic Circuit Design, 4E McGraw-Hill

N-Channel JFET i-v Characteristics Transfer Characteristics Output Characteristics Microelectronic Circuit Design, 4E McGraw-Hill

N-Channel JFET i-v Characteristics (cont.) For all regions : In cutoff region: In Triode region: In pinch-off region: Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill P-Channel JFET Polarities of n- and p-type regions of the n-channel JFET are reversed to get the p-channel JFET. Channel current direction and operating bias voltages are also reversed. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill JFET Circuit Symbols JFET structures are symmetric like MOSFETs. Source and drain determined by circuit voltages. Microelectronic Circuit Design, 4E McGraw-Hill

JFET n-Channel Model Summary Microelectronic Circuit Design, 4E McGraw-Hill

JFET p-Channel Model Summary Microelectronic Circuit Design, 4E McGraw-Hill

N-channel JFET Capacitances and SPICE Modeling CGD and CGS are determined by depletion-layer capacitances of reverse-biased pn junctions forming gate and are bias dependent. Typical default values used by SPICE: Vp = -2 V l = CGD = CGD = 0 Transconductance parameter BETA BETA = IDSS/VP2 = 100 mA/V2 Microelectronic Circuit Design, 4E McGraw-Hill

Biasing JFET and Depletion-Mode MOSFET: Example N-channel JFET Depletion-mode MOSFET Assumptions: JFET is pinched-off, gate-channel junction is reverse-biased, reverse leakage current of gate, IG = 0 Microelectronic Circuit Design, 4E McGraw-Hill

Biasing JFET and Depletion-Mode MOSFET: Example (cont.) Analysis: Since VGS = -13.1 V is less than VP= -5 V, VGS = -1.91 V and ID = IS = 1.91 mA. Also, VDS > VGS -VP. Hence pinch-off region assumption is correct and gate-source junction is reverse-biased by 1.91V. Q-pt: (1.91 mA, 6.27 V) Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill End of Chapter 4 Microelectronic Circuit Design, 4E McGraw-Hill Chap 3 -68

Microelectronic Circuit Design, 4E McGraw-Hill HW4 4.34 4.79 4.118 Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill Coulomb’s law The torsion balance, also called torsion pendulum, is a scientific apparatus for measuring very weak forces, usually credited to Charles-Augustin de Coulomb, who invented it in 1777, but independently invented by John Michell sometime before 1783. Its most well-known uses were by Coulomb to measure the electrostatic force between charges to establish Coulomb's Law, and by Henry Cavendish in 1798 in the Cavendish experiment to measure the gravitational force between two masses to calculate the density of the Earth, leading later to a value for the gravitational constant. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill The torsion balance consists of a bar suspended from its middle by a thin fiber. The fiber acts as a very weak torsion spring. If an unknown force is applied at right angles to the ends of the bar, the bar will rotate, twisting the fiber, until it reaches an equilibrium where the twisting force or torque of the fiber balances the applied force. Then the magnitude of the force is proportional to the angle of the bar. The sensitivity of the instrument comes from the weak spring constant of the fiber, so a very weak force causes a large rotation of the bar. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill In Coulomb's experiment, the torsion balance was an insulating rod with a metal-coated ball attached to one end, suspended by a silk thread. The ball was charged with a known charge of static electricity, and a second charged ball of the same polarity was brought near it. The two charged balls repelled one another, twisting the fiber through a certain angle, which could be read from a scale on the instrument. By knowing how much force it took to twist the fiber through a given angle, Coulomb was able to calculate the force between the balls. Determining the force for different charges and different separations between the balls, he showed that it followed an inverse-square proportionality law, now known as Coulomb's law. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill To measure the unknown force, the spring constant of the torsion fiber must first be known. This is difficult to measure directly because of the smallness of the force. Cavendish accomplished this by a method widely used since: measuring the resonant vibration period of the balance. If the free balance is twisted and released, it will oscillate slowly clockwise and counterclockwise as a harmonic oscillator, at a frequency that depends on the moment of inertia of the beam and the elasticity of the fiber. Since the inertia of the beam can be found from its mass, the spring constant can be calculated. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill Coulomb first developed the theory of torsion fibers and the torsion balance in his 1785 memoir, Recherches theoriques et experimentales sur la force de torsion et sur l'elasticite des fils de metal &c. This led to its use in other scientific instruments, such as galvanometers, and the Nichols radiometer which measured the radiation pressure of light. In the early 1900s gravitational torsion balances were used in petroleum prospecting. Today torsion balances are still used in physics experiments. Microelectronic Circuit Design, 4E McGraw-Hill

Microelectronic Circuit Design, 4E McGraw-Hill In 1987, gravity researcher A.H. Cook wrote: The most important advance in experiments on gravitation and other delicate measurements was the introduction of the torsion balance by Michell and its use by Cavendish. It has been the basis of all the most significant experiments on gravitation ever since. Microelectronic Circuit Design, 4E McGraw-Hill