KIT – Universität des Landes Baden-Württemberg und nationales Forschungszentrum in der Helmholtz-Gemeinschaft KIT, Institut für Prozessdatenverarbeitung und Elektronik M. Caselle M.Caselle MOS transistor & introduction to analog layout KSETA – KIT-Center Elementary Particle and Astroparticle Physics. 06 February 2014

KIT, Institut für Prozessdatenverarbeitung und Elektronik 2 BJT and CMOS transistors Fabrication steps of a FET and BJT  Current gain: Ic =  * Ib BJT transistor MOS transistor P-substrate S G D n+n+ n+n+ Transconductance : Ids = gm * Vgs S D I DS G V GS MOSBJT

KIT, Institut für Prozessdatenverarbeitung und Elektronik 3 n-MOS Field Effect Transistor L eff L Drawn MOS transistor (3D view) MOS transistor (n-type) – front section Source Drain Gate P-substrate n+n+ n+n+ S G D n+n+ n+n+ n + regions Metal Oxide (dielectric) Semiconductor (substrate) MOS transistor (p-type) – front section N-substrate S G D p+p+ p+p+ MOS Complementary MOS (CMOS) technologies, both n-MOS and p-MOS transistors are available W eff KSETA, Karlsruhe 26 February 2013 – M. Caselle Three terminals device (Source, Drain and Gate)

KIT, Institut für Prozessdatenverarbeitung und Elektronik 4 MOS transistor (n-type) MOS interface  capacitance vs. substrate Drain and source n + regions  diode vs. substrate G S D NMOS electrical symbol Electrical considerations: Drain and Source will work as two independent diodes with anode connected to bulk If V S < 0V and/or V D <0  this suggest that V S and V D must be ≥ 0V no current flow between Source and DrainIf V G = 0V What about the MOS interface behaviour …. ? n-MOS Field Effect Transistor (II) KSETA, Karlsruhe 26 February 2013 – M. Caselle Substrate at 0V

KIT, Institut für Prozessdatenverarbeitung und Elektronik 5 MOS interface – (I DS vs. V gs ) Characteristics Drain and Source are connected through with a conductive channel V TH V GS I DS P-substrate S G D n+n+ n+n+ -+ V G < 0 Hole accumulation S D P-substrate S G D n+n+ n+n+ Depletion region --+ V G > Negative ions S D + - P-substrate S G D n+n+ n+n Inversion layer Free electrons V G > V TH > 0 (threshold voltage) S D e-e- e-e- e-e- OFF ON KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 6 MOS interface – summarize Drain and Source are connected through with a conductive channel P-substrate S G D n+n+ n+n+ -+ V G < 0 Accumulation region P-substrate S G D n+n+ n+n+ Depletion region --+ V G > P-substrate S G D n+n+ n+n Inversion layer V G > V TH > 0 (threshold voltage) KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 7 n-MOS interface – (I DS vs. V DS ) Characteristic Linear or triode region V DS I DS V GS3 V GS2 V GS1 V DS close to zero V GS3 > V GS2 > V GS1 > V TH -+ S V D > 0 P-substrate n+n+ n+n V G > V TH S D S D MOSFET as a controlled linear resistor Ron G Channel modulation Typical value few hundred Ohms Thickness of the free electrons region depends on V GS S D V G > V TH P-substrate n+n+ n+n Inversion layer Free electrons KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 8 V DS Large VDS V DS1 = V GS1 - V TH I ds1 High resistance Saturation region V GS2 V GS1 I ds2 I ds3 V GS3 n-MOS interface – (I DS vs. V DS ) Characteristic -+ S V D > 0 P-substrate n+n+ n+n V G > V TH Linear or triode region Channel modulation V D > 0 I DS S D G P-substrate n+n+ n+n+ Saturation region -+ V G > V TH Channel pinch-off (point with no free charges inside) KSETA, Karlsruhe 26 February 2013 – M. Caselle S D V G > V TH I DS Drain Source I DS R out I ds = g m * V GS V DS > V GS - V TH

KIT, Institut für Prozessdatenverarbeitung und Elektronik 9 I DS vs. V DS working regions High resistance Saturation region V DS I DS V GS3 V GS2 V GS1 Linear region V GS ~ 0V V DS any values S D I DS G V GS V DS MOS works as a switch (ON) (low serial resistance) D S V GS > V TH V DS > V GS - V TH D S MOS works as a switch (OFF) (high resistance of ten/hundred megaohms) Digital Circuit Analog Circuit V GS > V TH and V DS ~ 0V KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 10 P-device is implemented in a N-type well (n-well) n-well The CMOS technology MOS transistor (n-type) Require P-substrate S G D n+n+ n+n+ MOS transistor (p-type) Require a N-substrate S G D p+p+ p+p+ CMOS technology is used in microprocessors, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, etc.. Complementary MOS (CMOS) is a technology for constructing integrated circuits In which way it is possible to merge two different transistor typologies on common substrate ? CMOS inverter (NOT logic gate) p-mos n-mos A  input signal Q  output signal Vss could be = 0V Few µm KSETA, Karlsruhe 26 February 2013 – M. Caselle P- substrate

KIT, Institut für Prozessdatenverarbeitung und Elektronik 11 n-MOS technology layout and physical implementation (I) Step 1 – n + drain/source region n + region (RX) Transistor channel Width 3D view Layout view n+n+ P- substrate Step 2 – drain/source metal contact Drain and Source metal contact (CA) Metal 1 3D view Layout view Source Drain n+n+ P- substrate Width KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 12 n-MOS technology layout and physical implementation (II) Step 3 – poly polygon as channel gate Transistor channel length Poly-silicon (conductive) 3D view Layout view Source Drain n+n+ Gate P- substrate Step 4 – active area Active area for n-transistor (green) n-MOS DONE P- substrate The MOS structure is automatically recognized by the active area rectangle 3D view Layout view Source Drain n+n+ n+n+ Gate W NMOS KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 13 p-MOS technology layout and physical implementation (III) Step 4 – p-MOS transistor Active area for p-transistor (brown) Note that the p-MOS width is increased 3D view Layout view W PMOS Source Drain Gate p+p+ p+p+ Step 5 – n-well region n-well 3D view Layout view Source Drain Gate p+p+ p+p+ W PMOS p-MOS DONE KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 14 CMOS technology layout and physical implementation (I) M1 M2 p-MOS n-MOS S D G S D V DD G M1 M2 IN OUT Schematic viewLayout view Combine the n-MOS with p-MOS. Note the different sizes W PMOS W NMOS KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 15 CMOS technology layout and physical implementation (II) S D G S D V DD G V GS M1 M2 IN OUT By poly connection (red) By metal 1 connection (blue) Schematic viewLayout view GND metal 1 (large to avoid a large ohmic voltage drop) VDD metal 1 (large to avoid a large ohmic voltage drop) KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 16 CMOS technology layout and physical implementation (III) S D G S D V DD G M1 M2 IN OUT Schematic view Layout view By metal 1 (blue) GND metal 1 VDD metal 1 By metal 1 (blue) By metal OUT IN KSETA, Karlsruhe 26 February 2013 – M. Caselle GND VDDOUT n+n+ n+n+ p+p+ p+p+ n-well p-substrate n-MOS p-MOS Poly-gate (red) 3D View

KIT, Institut für Prozessdatenverarbeitung und Elektronik 17 Example of layout design C E A N B F M1M1 M2M2 M3M3 E C N F 1. Drawing the diffusion polygon 2. Drawing the poly-gate polygons M 1, M 2 and M 3 KSETA, Karlsruhe 26 February 2013 – M. Caselle A B N E F Metal 1 Aluminium or copper 4. Drawing the metal 1 connections Final layout 3. Drawing the poly - metal contacts C M1M1 M2M2 M3M3

KIT, Institut für Prozessdatenverarbeitung und Elektronik 18 Introduction to analog building blocks S D G V GS V DS V DD M1 IN OUT R S D G V GS V DS V DD M1 IN OUT R G V GS M1 S D V DD IN 1 OUT S D V GS IN 2 Common drain Common source Differential pair M2 RR KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 19 Common source (single stage analog amplifier) S D G V GS V DS V DD M1 IN OUT R V IN V OUT VDD V TH MOS in saturation V IN1 MOS OFF MOS in Linear region KVL: VOUT = VDD –R*I D IDID S D G V DD M1 IN OUT R V IN is low < V TH MOS is switch OFF I D = 0  VOUT = VDD S D G V DD IN OUT R r on V IN >> V TH MOS in linear r on very low  close a short VOUT = VDD – gm * V IN * (R) A M1 V IN > V TH MOS in saturation I D = gm* V IN S D G V DD IN OUT R IDID V OUT = - A * V IN A A B B C C KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 20 Single stage amplifier S D G V GS V DS V DD M1 IN OUT R IDID V IN V OUT VDD V TH MOS in saturation MOS OFF MOS in Linear region time Polarization voltage offset Analog signal to be amplified A* V IN 0 VBIAS KSETA, Karlsruhe 26 February 2013 – M. Caselle r M2 r M1 Gain = -gm 1 * (r M1 ||r M2 ) In many CMOS technologies, it is difficult to fabricate resistors with tightly-controlled values or a reasonable physical size. It is desirable to replace the R with a MOS transistor (current mirror) S D G V DD M1 IN OUT M2 p-MOS current source for high Resistance V bias IDID

KIT, Institut für Prozessdatenverarbeitung und Elektronik 21 Common drain (Source follower) Used as voltage buffer or level shifter V OUT =~ V IN Output follows the input IDID S D G V GS V DD M1 IN OUT R R IN  very high R OUT  very low V IN V OUT V TH MOS in saturation V IN1 MOS OFF V IN is low < V TH MOS is switch OFF I D = 0  V OUT = 0 S D G V GS V DD M1 IN OUT R S D G V GS V DD M1 IN OUT R V OUT = R * I D (KVL) IDID V OUT = R * gm (V IN -V OUT ) A A B B KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 22 Source follower CMOS technology S D G V GS V DD M1 IN OUT R S D G V GS V DD M1 IN OUT n-MOS current source M2 Basic rules  Follower MOS M1 (W/L) 1 >> mirror current M2 (W/L) 2 M1 M2 VDD GND IN High Resistance High gm gm  W M1 /L V bias W M1 W M2 L M1 L M2 KSETA, Karlsruhe 26 February 2013 – M. Caselle CMOS technology

KIT, Institut für Prozessdatenverarbeitung und Elektronik 23 Differential pair, why ? (Case 1) S D G V DD M1 IN OUT R Clock Line to line capacitance Clock line Analog signal line Corruption of the signal due to parasitic coupling line Solution …. M2 IN M1 IN Clock Reduction of coupling noise by differential operation Analog signal line Clock line KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 24 Differential pair, why ? (Case 2) S D G V DD M1 IN OUT R Analog signal line Effect of supply noise on a single-ended amplifier Noise from power supply Solution …. M2 IN M1 IN V DD V OUT = V OUT1 – V OUT2  Differential circuit V OUT1 V OUT2 KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 25 Differential pair V DD M2 V IN2 M1 V IN1 V OUT1 V OUT2 IDID R R I1I1 I2I2 If V IN1 –V IN2 V OUT1 = VDD & V OUT2 = V DD - R*I D M2 V IN2 M1 V IN1 V OUT1 V OUT2 IDID R R I 2 = I D A M2 V IN2 M1 V IN1 V OUT1 V OUT2 IDID R R I 1 = I D If V IN1 –V IN2 >> 0  M 1 is ON and M 2 OFF  I 1 =0 and I 2 =I D => V OUT1 = V DD -R*I D & V OUT2 = VDD B M2 V IN2 M1 V IN1 V OUT1 V OUT2 IDID R R I1I1 I2I2 Middle V IN1 –V IN2  M 1 is ON and M 2 ON  I D = I 1 + I 2 => V OUT1 = V DD -R*I 1 & V OUT2 = V DD -R*I 2 C V IN1 – V IN2 V OUT V DD VDD – R*I D V OUT1 V OUT2 A B C KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 26 Differential pair (II) V out = V out2 – V out1 = gm 1,2 * (R) * (V IN1 -V IN2 ) Gain KSETA, Karlsruhe 26 February 2013 – M. Caselle V DD M2M1 V OUT1 V OUT2 IDID I1I1 I2I2 CMOS technology R R V IN1 – V IN2 V OUT V DD A B VDD – R*I D V OUT1 V OUT2 A B A B Output time

KIT, Institut für Prozessdatenverarbeitung und Elektronik 27 Simple implementation of two-stage op-amp (II) +-+- V IN V OUT Stage 1 Input stage diff. pair Stage 2 High gain stage V IN V OUT V bias M5 M2M1 V IN IDID I1I1 I2I2 V DD M3 M4 V OUT Output common source current sources Input stage differential pair C N-well P-mos current mirror n-MOS diff. pair M2 M1 M3 M4 V bias GND VDD Current source for diff. pair M5 C V IN+ V IN- KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 28 ASIC implementation (I) Matrix control input 16 Output one for each pixel Readout Analog cell for pmoslvt pixel Pixel cell Digital logic VDDA GNDA KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 29 Analog readout for “pmoslvt” & “pmosdg” pixel cells IBias GNDA C PAD Detector -VBias First device (PMOS in follower conf.) Ipix C Line GNDA 1. Pixel cell current Source 3. CMOS switch 2. Follower (NMOS) Drop voltage level N ++ V DD ring KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 30 Conclusion  n-MOS Field Effect Transistor  Introduction CMOS technology  CMOS layout design  Introduction at analog circuits

KIT, Institut für Prozessdatenverarbeitung und Elektronik 31 Radiation effects in MOS device – basic concepts Bird’s beak Field oxide Parasitic MOS Parasitic channel Thin oxide (gate) Main MOS The gate voltage control is lost  The Parasitic MOSs switch ON the structure permanently Solution is the Enclosed Layout Transistor (ELT) Efficiently prevent source-drain leakage currents Charge particle KSETA, Karlsruhe 26 February 2013 – M. Caselle

KIT, Institut für Prozessdatenverarbeitung und Elektronik 32 Enclosed Layout N-MOSFETs Source enclosed by gate (channel) so that no any parasitic leakage currents can through from Source to Drain Regular P MOS ELT N MOS VDD GND S D G S D V DD G M1 M2 IN OUT Inverter in rad-hard layout Double fingers MOS KSETA, Karlsruhe 26 February 2013 – M. Caselle