CoolRunner ™ -II Low Cost Solutions

Quick Start Training Introduction CoolRunner-II system level solution savings Discrete devices vs. CoolRunner-II ASIC vs. CoolRunner-II CoolRunner-II design tools – CoolRunner Reference Designs – CoolRunner-II Design Kit – Software Cost summary

CoolRunner-II System Level Savings File Number Here

Quick Start Training System Integration Advantage

Quick Start Training Xilinx CPLD Feature Comparison

Quick Start Training System Level Savings High volume economies of scale – Single chip for multiple system solutions Increased volume means reduction in all related costs Reference designs – Minimize risk and shorten design cycles Lowest cost per I/O On the Fly (OTF) Reconfiguration – Two devices for the price of one

Quick Start Training High Volume Economy of Scale Single chip for multiple system solutions – Speed, low power consumption and voltage translation in a single device – Reduces the cost for multiple manufacturing flows and mask sets Volume discounts on fixed costs (packages and die) – Significantly reduces cost structure due to high run rates Single product family allows focused multi site usage model

Quick Start Training Lowest Cost Per I/O Reduce risk of changing marketing feature requirements – Extra I/O lend helping hand to feature creep No need to pay for extra logic – Stay in the device that best fits your design – When all you need is more I/O - why pay for a larger device?

Quick Start Training Price per I/O vs. Lattice ispMACH CoolRunner-II saves you money over the competition For each device density, the slowest speed, least expensive package with max I/O

Quick Start Training Price per I/O vs. Altera 7000B CoolRunner-II saves you money over the competition For each device density, the slowest speed, least expensive package with max I/O

Quick Start Training On the Fly (OTF) Reconfiguration Two devices for the price of one – On power up, the CPLD performs one function – When system is configured, CPLD performs system functions Personality daughter card solution – Use OTF feature to enable multi-function modes on a single daughter card After power-up function, re-program for specific personalities

CoolRunner-II vs. Discrete Cost File Number Here

Quick Start Training Discrete Device Cost vs. CoolRunner-II Schmitt inputs – $9.50 Voltage translation – $2.46 I/O standard translation – $6.26 Total $18.22 CoolRunner-II 128mc device – With 80 I/O – Schmitt inputs – Voltage translation – I/O translation PLUS – Extra Logic – Re-programmable Total $ % less

Quick Start Training Discrete Device Area vs. CoolRunner-II Schmitt inputs – 8.7 x 8.7 mm (75.7mm 2 ) Voltage translation – 12 x 6mm (72mm 2 ) I/O standard translation – 12 x 6mm (72mm 2 ) Total 220mm 2 24mm 2 more space CoolRunner-II 128mc device – 14 x 14mm (196mm 2 ) Total area 196mm 2

Quick Start Training Discrete Device Pin Usage vs. CoolRunner-II Schmitt inputs – 20 pins with 6 outputs Voltage translation – 48 pins with 16 outputs I/O standard translation – 48 pins with 9 outputs Total usable pins 31 of 108 (29% usage) CoolRunner-II 128mc device – XC2C128-4VQ100C Total usable pins 80 of 100 (80% usage)

Quick Start Training Discrete Device Power Consumption vs. CoolRunner-II Schmitt inputs – 0.05mA Voltage translation – 0.1mA I/O standard translation – mA Total power consumption ~ 50mA CoolRunner-II 128mc device – With 4 16 bit counters, schmitt inputs, voltage translation and I/O translation at 50MHz = 6.8mA – This power calculation is without DataGATE Total power consumption ~6.8mA

Quick Start Training DataGATE Advantages at No Additional Cost Individual input pins can be shut off without powering down the device Reduces power – Does not toggle pins in a don’t care state Simplifies system or part debug – Helps isolate certain signals or pins at will Aids in hot plugging system boards – e.g., into a backplane

Quick Start Training DataGATE - Ultimate Low Power Standby With DataGATE enabled, current consumption reduced from 3.37mA down to 70uA ! (slot machine design example)

Quick Start Training Discrete Device Routing & Layout vs. CoolRunner-II Multiple devices increase R&D and production costs – R&D costs PCB layout is more complex due to more routing – Routing is internal to CPLD Design costs increase due to increased time in design – Single chip design in high level design language – Test and assembly costs Functional testing cost is on a per device adder – Single chip testing with built in JTAG Assembly cost is on a per device adder – Single chip stocking and assembly

Quick Start Training Multi vs. Single Chip Cost Comparison Note: Estimated results normalized to one

Quick Start Training Summary of Discrete Devices vs. CoolRunner-II Discrete devices – 3 devices – Total $18.22 – Total 220mm 2 – Total usable pins 31 of 108 CoolRunner-II – Single device – Total $8.00 – Total area 196mm 2 – Total usable pins 80 of 100 – Lower power PLUS – Extra logic – Re-programmable

CoolRunner-II vs. ASIC Cost File Number Here

Quick Start Training Product Unit Volume Dynamics New products go to high volume quickly and have short product life cycles 1 Years in Production 1 million units CellularPCGamesTV Volume PDA 2

Quick Start Training ASIC Development Takes Too Long! Short product life cycles limit ASIC usage – Multiple ASIC re-spins can leave little time to run in production or completely miss the market window – ASICs are not re-programmable and do not allow last minute design revision changes Smaller than expected run rates may not justify the ASIC development and NRE costs CPLDs allow customers to address market and design changes quickly!

Quick Start Training Short Product Life Limits ASICs CPLDs are the quick Time To Market solution saving revenue Years in Production Volume 1 Cellular PC Games TV PDA 2 Short life cycle products need quick design times to meet tight market windows ASIC development and re-spin delays can miss a major part of the production cycle resulting in lost revenue ASIC delays

CoolRunner-II Quick Design Tools File Number Here

Quick Start Training CoolRunner Reference Designs Shorten design cycle time – Eliminate code porting costs for next design cycle Re-use of HDL is reliable and stable Minimize design risk by using reference designs – Availability of reference designs prepares you for unexpected system changes Update main processor but it does not incorporate correct bus interface Further improve customer’s Time To Market – Proven designs for quick turn requirements

Quick Start Training Faster Designs with FREE CoolRunner Reference Designs Free VHDL design code: Coming soon

Quick Start Training CoolRunner-II Design Kit A complete, easy to use CoolRunner-II CPLD Design Kit – Logic designers new to CPLDs – CPLD designers new to Xilinx – ASIC designers not aware of CoolRunner-II advanced features Simple and inexpensive demo board ready to use – Battery or AC outlet power source – Inexpensive parallel printer cable for programming – LED's for simple testing – Dual in line I/O header for easy connections – Jumpers for easy modifications – Multiple device selection on a single board

Quick Start Training CoolRunner-II Design Kit

Quick Start Training Online Software Solutions Free WebFITTER™ – Easily fit designs for all Xilinx CPLDs online – Accepts VHDL/verilog/abel & standard netlists – Simplepld & competitive conversions – Fitting & timing reports – Online price quotes for purchasing the best PLD silicon solution Free ISE 6.1i WebPACK™ – Downloadable desktop solution – HDL / ABEL synthesis & simulation – JTAG & 3rd party EDA support – Supports all Xilinx CPLD families – Supports Spartan-II, IIE & 3, Virtex-E & II (up to 300K gates) FPGAs – Links to online purchasing

Quick Start Training CoolRunner-II Cost Summary Lowest overall system cost Single chip CPLD advantages over multiple discrete chips Re-programmable CPLD advantages over ASIC Advanced features for free Design faster using online software, reference designs and design kits

Quick Start Training One CPLD Solution for All Designs Handheld, Portable Equipment * Estimated 128 macrocell device, Eight 16-bit 50MHz High Performance 3.0ns t PD, f max 385MHz Improved features Low Cost 0.18µ = small die size Lowest cost packaging Lowest Power 12mW* ~20 u A typical stand-by Storage Systems, Routers Set-Top Box, Cell Phone