Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 15, 2013 Memory Periphery

Today Memory Periphery Sensing Driving Decode Penn ESE370 Fall DeHon 2

Sensing Penn ESE370 Fall DeHon 3

4 SRAM Memory bit

Simulation W access =20 Penn ESE370 Fall DeHon 5

Sense Small Swings What do we have to worry about? Penn ESE370 Fall DeHon 6

Sense Small Swings Variation –Shift where inverter trip point is Systematic shifts that effect both lines –“Common mode” noise –E.g. Noise Voltage droop Penn ESE370 Fall DeHon 7

Two Sense Amps 1.Clocked / Regenerative Feedback 2.Not clocked / Differential Sense Amp Goal: amplify small signal difference reject common mode noise Penn ESE370 Fall DeHon 8

Differential Sense Amp Goal: –Reject common shift Penn ESE370 Fall DeHon 9

Warmup What does this do? How do we size transistor? Penn ESE370 Fall DeHon 10

Voltage Controlled Consider Vctrl as an analog input between 0 and Vdd-Vth What does this do? How does the voltage on V ctrl control operation? Penn ESE370 Fall DeHon 11

DC Transfer Penn ESE370 Fall DeHon 12

Idea Control Resistance to control trip point Set trip point based on second line Q: how set Vctrl? Penn ESE370 Fall DeHon 13

Differential Sense Amp Penn ESE370 Fall DeHon 14

What does this do? Output when: –In=Gnd? –In=Vdd? –Transfer curve? Penn ESE370 Fall DeHon 15

“Inverter” Input high –Ratioed like grounded P Input low –Pulls itself up –Until V dd -V TP Penn ESE370 Fall DeHon 16

DC Transfer Function Penn ESE370 Fall DeHon 17

Differential Sense Amp Penn ESE370 Fall DeHon 18

Diffamp Transfer Function in=/in, looks like “inverter” Deliberately low gain in mid region Ideal might be flat? Penn ESE370 Fall DeHon 19

Differential Sense Amp “Inverter” output controls PMOS for second inverter Sets PMOS operating point –Voltage controlled resistance –Sets trip point Penn ESE370 Fall DeHon 20

Differential Sense Amp What happens when o /in > in? o /in < in? Penn ESE370 Fall DeHon 21

Differential Sense Amp View: –Current mirror –Biases where inverter operating Penn ESE370 Fall DeHon 22

Differential Sense Amp View: – adjusting the pullup load resistance –Changing the trip point for “inverter” Penn ESE370 Fall DeHon 23

DC Transfer /in with in=0.5V Penn ESE370 Fall DeHon 24

DC Transfer Various in Penn ESE370 Fall DeHon 25

DC Transfer Various in What is trip point when: In=0.3V? In=0.4V? In=0.5V? In=0.6V? In=0.7V? Penn ESE370 Fall DeHon 26

After Inverter Penn ESE370 Fall DeHon 27

Ramp 50mV Offset Penn ESE370 Fall DeHon 28

Closeup 50mV Offset Penn ESE370 Fall DeHon 29

Differential Sense Amp Does need to be sized There is a ratioed logic effect here Penn ESE370 Fall DeHon 30

Regenerative Feedback Penn ESE370 Fall DeHon 31

Connect to Column Equalize lines during precharge Penn ESE370 Fall DeHon 32

Singled-Ended Read Penn ESE370 Fall DeHon 33

5T SRAM Penn ESE370 Fall DeHon 34

Single Ended Given same problems –How sense small swing on single-ended case? Penn ESE370 Fall DeHon 35

Single Ended Need reference to compare against Want to look just like bit line Equalize with bit line Penn ESE370 Fall DeHon 36

Split Bit Line Split bit-line in half Precharge/equalize both Word in only one half –Only it switches Amplify difference Penn ESE370 Fall DeHon 37

Open Bit Line Architecture For 1T DRAM Add dummy cells Charge dummy cells to V dd /2 “read” dummy in reference half Penn ESE370 Fall DeHon 38

Memory Bank Penn ESE370 Fall DeHon 39

Row Select Penn ESE370 Fall DeHon 40

Memory Bank Penn ESE370 Fall DeHon 41

Row Select Logically a big AND –May include an enable for timing in synchronous Penn ESE370 Fall DeHon 42 How many transistors (per address bit)?

How tall is a row? Side length for cell of size: – – – Penn ESE370 Fall DeHon 43

44 How tall is an AND? Penn ESE370 Fall DeHon

Row Select How can we do better? –Area –Delay –Match to pitch of memory row Penn ESE370 Fall DeHon 45

Row Select Compute inversions outside array –Just AND appropriate line (bit or /bit) Penn ESE370 Fall DeHon 46

Row Select Share common terms Multi-level decode Penn ESE370 Fall DeHon 47

Row Select Same number of lines Half as many AND inputs inside the row Penn ESE370 Fall DeHon 48

Row Select: Precharge NAND Penn ESE370 Fall DeHon 49

Row Select: Precharge NOR Penn ESE370 Fall DeHon 50

Bus Drivers Penn ESE370 Fall DeHon 51

Memory Bank Penn ESE370 Fall DeHon 52

Tristate Driver Penn ESE370 Fall DeHon 53

Tri-State Drivers Penn ESE370 Fall DeHon 54

Idea Minimize area of repeated cell Compensate with periphery –Amplification (restoration) Match periphery pitch to cell row/column –Decode –Sensing –Writer Drivers Penn ESE370 Fall DeHon 55

Admin Monday: in Detkin Lab –Read lab2 assignment before coming to class Tuesday: Proj2 Milestone due Wednesday: Lecture Penn ESE370 Fall DeHon 56