Reconfigurable Hardware in Wearable Computing Nodes Christian Plessl 1 Rolf Enzler 2 Herbert Walder 1 Jan Beutel 1 Marco Platzner 1 Lothar Thiele 1 1 Computer Engineering Lab 2 Electronics Lab ETH Zurich, Switzerland

Outline Characteristics of Wearable Computers Hardware architectures Reconfigurable Devices Use of Reconfigurable HW in Wearable Computing Wearable Unit with Reconfigurable Modules (WURM) Case studies, Prototypes Conclusions

Wearable Computing Systems… … as we see it Distinctive Features: embedded distributed heterogeneous connected via body area network Design characteristics: multi-mode performance energy awareness high flexibility / adaptability

The Quest for an Optimal Architecture for Wearable Computers Conflicting goals: high-performance low-power flexibility Performance 1/Power consumption Flexibility DSP ASIC CPU RC

Reconfigurable (RC) Devices - Hardware Predominant device: FPGA CLBs (Configurable Logic Blocks) Routing Ressources IOBs (Input / Output Blocks)

RC Devices – Application Domains RC most efficient for: regular and parallelizable operations bit-level operations custom bitwidths Examples: Mencer et al [ICASSP’98]: IDEA encryption: Stitt et al [FCCM’02]: Energy savings of 71% on a set of embedded benchmarks (measured on Triscend E5) Mobile multimedia (IMEC Gecko plattform) TypeDeviceMbit/sMbit/Ws CPUStrongARM SA DSPTI TMS320C6x FPGAXilinx XC4020XL DSP Crypto Communication

Use for RC in Wearable Computers ASIC on demand application specific coprocessors available locally, or sent via wireless network new circuits provided when new applications arise Adaptive interfaces device provides generic I/O pins and transceivers protocol for communication is not fixed, but software defined in FPGA Interface might be simple or complex –SPI, I2C, Ethernet, RS232 (simple) –IP, UDP, TCP (complex) Offload Parts of communication protocol handling

Use for RC in Wearable Computers (2) ADPCM Compression Feature Extract- tion & Analysis Arm motion sensing Main Module 170 kbit/s Main Module 3 bit/s Main Module 120 bit/s Harddisk Context Engine Gyro sensors 706 kbit/s I2C

Research Issues – What’s needed HW Plattforms: RC partially reconfigurable RC fast reconfigurable CPU – RC interface fast and versatile SW Tools: Synthesis / compilation –abstraction for hw tasks –creation of partially reconfigurable tasks RC Operating System –multitasking of RC –interfaces hw/sw

WURM - Wearable Unit with RC Modules WURM Hardware Architecture CPU for: –legacy C-code, binary only code –low-intensity, background tasks RC unit for: –high-performance tasks –low-power tasks

WURM - Hardware Prototype XESS board, multitude of I/O interfaces Soft CPU (LEON, 32bit SPARC) BTnode (custom Bluetooth Module)

WURM - SW Architecture WURM OS layer: loading, placing and scheduling of hw/sw tasks inter-task communication, task I/O sw tasks handled by realtime os CPURC WURM-OS

Case Study 1: ASIC on Demand Audio stream player Complete WURM on FPGA LEON 32bit SPARC soft-CPU core RTEMS (real-time OS) ADPCM decoder (Intel DVI compliant) Ethernet CPU (LEON core, RTEMS) PCM/ ADPCM Player FPGA PCM / ADPCM audio data dynamic reconfiguration

Case Study 2: Adaptive Interface Bluetooth/Ethernet-Bridge IP access point for WURM modules via Bluetooth Minimal TCP/IP stack Ethernet MAC BTnode Bluetooth module ((( ))) Hard- ware IP stack RS232Ethernet IP Network

Conclusions & Next Steps Concept for reconfigurable hardware in wearable computing Experimental status: first implementation of partially reconfigurable WURM prototype including BTnode tool for creation of partially reconfigurable tasks multi-tasking on RC demonstrated Next Steps: autonomous reconfiguration, receive tasks over network task and resource management in WURM OS

Backup

BTnode