156 / MAPLD 2005 Rollins 1 Reducing Energy in FPGA Multipliers Through Glitch Reduction Nathan Rollins and Michael J. Wirthlin Department of Electrical and Computer Engineering Brigham Young University Provo, UT This work was supported by the NASA Earth-Sun System Technology Office as sub-contract with USC-ISI

156 / MAPLD 2005 Rollins 2 FPGAs’ High Power Consumption Flexibility and reprogrammability result in greater power consumption relative to ASICs Static power is insignificant compared to dynamic power consumption Dynamic power consumption: P avg = ½ Σ C n ·f n ·V 2 n є nets

156 / MAPLD 2005 Rollins 3 FPGAs’ High Power Consumption f n term represents the net switching activity Some net switching activity is unproductive: glitches Large amount of dynamic switching power wasted in glitches Goal: Lower energy by reducing the amount of glitching

156 / MAPLD 2005 Rollins 4 FPGA Glitching Example LUT 4 ABCDOUT A B C D 0 Glitching caused by unequal logic and interconnect delays

156 / MAPLD 2005 Rollins 5 FPGA Glitching Example LUT 4 ABCDOUT A B C D 1 1 Glitching caused by unequal logic and interconnect delays

156 / MAPLD 2005 Rollins 6 FPGA Glitching Example LUT 4 ABCDOUT A B C D Glitch Glitching caused by unequal logic and interconnect delays

156 / MAPLD 2005 Rollins 7 FPGA Glitching Example LUT 4 ABCDOUT A B C D Glitch 1 Glitching caused by unequal logic and interconnect delays

156 / MAPLD 2005 Rollins 8 FPGA Glitching Example LUT 4 ABCDOUT A B C D Glitch 1 1 Glitching caused by unequal logic and interconnect delays

156 / MAPLD 2005 Rollins 9 Power Classification Design Static Power: divide the total static power of the device by the relative size of the circuit Total Static Power / (Circuit LUTs / Total LUTs) Dynamic Glitching Power: % of signal glitches to total transitions is used to divide dynamic power into dynamic glitching and useful dynamic power Useful Dynamic Power: the “useful” transitions of the circuit

156 / MAPLD 2005 Rollins 10 Reduce Glitches with Pipelining Pipelined designs have less logic and interconnect between registers Pipelining causes long routes to be broken up Pipelining in FPGAs can come at little additional cost

156 / MAPLD 2005 Rollins 11 Pipelined Multiplier Long carry chain paths of multiplier stages are ideal for pipelining Pipelining gradually inserted in multipliers of different bit widths: –4x4 –8x8 –16x16 –32x32

156 / MAPLD 2005 Rollins 12 Multiplier Power Classification 12.5% 0.2% 87.3% 4-Bit 46.6% 0.2% 53.2% 8-Bit 16-Bit 68.2% 0.1% 31.7% 32-Bit 75.9% 0.0% 24.1% Dynamic Glitch Power Useful Dynamic Power Static Power

156 / MAPLD 2005 Rollins 13 Reduce Glitches with Pipelining Pipelining reduces glitching and lowers power

156 / MAPLD 2005 Rollins 14 Extreme Pipelining: Digit-Serial In an FPGA an NxN array multiplier can have N pipeline stages A digit-serial multiplier provides pipelining at a smaller granularity Digit-serial operations can increase throughput – but also increase latency Different digit sizes of digit-serial multiplier used: 1, 2, 4, 8, 16, 32

156 / MAPLD 2005 Rollins 15 Pipelined vs. Digit-Serial Multiplier: Total Power Consumption Digit-serial multiplier has almost no glitching - dynamic glitching power accounts for < 1% of total power Array Multipliers Digit-serial Multipliers

156 / MAPLD 2005 Rollins 16 Operation Energy Most studies focus on quantifying circuit design power only – often energy is a more useful metric Four metrics can be used for energy consumption –Energy per Operation –Energy Delay –Energy Throughput –Energy Density

156 / MAPLD 2005 Rollins 17 Pipelined vs. Digit-Serial Multiplier: Energy Per Operation Array Multipliers Digit-serial Multipliers Quantifies the amount of energy required to complete a single operation (in nJ) E op = P·t clk ·n

156 / MAPLD 2005 Rollins 18 Pipelined vs. Digit-Serial Multiplier: Energy Delay Array Multipliers Digit-serial Multipliers Combines the energy efficiency and speed of an operator into a single parameter (in nJ ns) E delay = P·t clk ·t min ·n

156 / MAPLD 2005 Rollins 19 Pipelined vs. Digit-Serial Multiplier: Energy Throughput Array Multipliers Digit-serial Multipliers Operation pipelined version of energy delay E thput = P·t clk ·t min ·δ

156 / MAPLD 2005 Rollins 20 Pipelined vs. Digit-Serial Multiplier: Energy Density Array Multipliers Digit-serial Multipliers Normalizes the amount of energy used to perform a single operation to the logic resources used E density = P·t clk /Area

156 / MAPLD 2005 Rollins 21 Pipelined vs. Digit-Serial Multiplier: Clock Energy Increase Array Multipliers Digit-serial Multipliers In contrasts to an ASIC, there is very little or no increase in clock energy as pipeline depths or digit sizes are increased

156 / MAPLD 2005 Rollins 22 Conclusions and Future Work Glitch power is often a significant percentage of total consumed power Up to 76% in an array multiplier Reducing glitching is essential for low power designs

156 / MAPLD 2005 Rollins 23 Conclusions and Future Work Pipelining is an effective way of reducing glitches Digit-serial multiplier almost eliminates glitches Reducing glitching by pipelining reduces power consumption Up to 96% in an array multiplier

156 / MAPLD 2005 Rollins 24 Conclusions and Future Work More information that just raw power consumption is required for effective low- power designs Different energy metrics can provide this extra information A high-level synthesis tool can use this information to produce low power designs