Petros OikonomakosBashir M. Al-Hashimi Mark Zwolinski Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-line Testability Metric Electronics and Computer Science University of Southampton, UK Electronic Systems Design Group

Motivation On-line testability and Self-checking design  High reliability requirements  Hostile environments  …but significant hardware and / or performance penalties High-level synthesis  Fast time-to-market  Fast and efficient design space exploration  Specification-driven optimisation at the highest level of abstraction High-level synthesis for on-line testability

Outline  Introduction  Physical and Algorithmic Duplication and Inversion-based Self-checking Design  High-level Synthesis Background  Implementation : Transforms, Metric, Algorithm  Synthesis and Simulation Results  Conclusion

Introduction  Self-checking design at the RTL : typical in industry  Self-checking design before high-level synthesis  Self-checking design after high-level synthesis Our approach : self-checking design within high-level synthesis!!!

Self-checking design CUT CUT* Comparator Duplication CUT INV(CUT) Comparator Inversion  CUT* : functionally equivalent to CUT  Fault secure by nature  INV(CUT) : functional “inverse” of CUT  Fault secure for arithmetic modules

Self-checking design Physical vs. Algorithmic Duplication Physical Duplication physically duplicated operators over 100% hardware overhead Algorithmic Duplication behaviourally duplicated operations possible significant hardware savings

Self-checking design Physical vs. Algorithmic Inversion Physical Inversion no advantage over duplication Algorithmic Inversion allied to algorithmic duplication possibly more hardware savings than algorithmic duplication

High-level synthesis background  behavioural HDL code  initial design  iterative refinement (optimisation loop)  driven by a cost function  based on available (scheduling, allocation) transformations  controlled by an algorithm

transform and data selection validity check High-level synthesis optimisation loop transformation valid? cost estimation perform transform?perform another transform? execution end y n y nyny n

Implementation - Transforms within the Multiple Objective Optimisation in Data and control path Synthesis (MOODS) High-level Synthesis Suite N #1 C1 #2 C2 Initial state

Implementation - Transforms within the Multiple Objective Optimisation in Data and control path Synthesis (MOODS) High-level Synthesis Suite N #1 C1 #2 C2 N+1 C3 #2´ N+2 != Applying an on-line test resource insertion transform

Implementation - Transforms within the Multiple Objective Optimisation in Data and control path Synthesis (MOODS) High-level Synthesis Suite N #1 C1 #2 C2 N+1 C1 #2´ != Optimising for area

Implementation - Transforms within the Multiple Objective Optimisation in Data and control path Synthesis (MOODS) High-level Synthesis Suite N #1 C1 #2 C2 N+1 C3 #2´ N+2 != Applying an on-line test resource insertion transform

Implementation - Transforms within the Multiple Objective Optimisation in Data and control path Synthesis (MOODS) High-level Synthesis Suite N C1 C2 C3 #1 #2 #2´ != Optimising for speed

Implementation - Metric  Overall cost function Cost=c 1 α 1 +c 2 α c n α n Enhancing the cost function to include on-line testability  α n+1 =T on-line =σ 1 P 1 +σ 2 P 2 (1-P 1 )+σ 3 [log(L -1 )+σ 4 ] P 1 : % of on-line testable operations P 2 : % average idle time availability L : average error latency σ 1,σ 2,σ 3,σ 4 : constants

Implementation - Algorithm  Simulated annealing  Choice between duplication and inversion based on clock period requirements  Area- and / or delay-oriented heuristics …more on MOODS : reference [7]

Experimental results 3-dimensional design space, on-line testability on the z-axis x-y plane : untestable designs  design space exploration area (slices) delay (ns) testability % area (slices) delay (ns) testability % area (slices) delay (μs) testability % tsengdiffeq qrs z z z x x x y y y

Experimental results The significance of design space exploration Optimisation SettingsResults Area (slices)Max Freq. CyclesTestability Area, delay146 48MHz 7 - Area, delay, testability165 (+13%) 4MHz 7 Inv (100%) Delay, testability172 (+17.8%) 38MHz 7 Dupl (100%) (tseng benchmark) optimum design depends on clock speed requirements the tool provides options  the designer makes decisions!

Experimental results Simulation  transparent fault injection and simulation, at the RTL  independent experiments, a single fault at a time  random faults, random inputs Results (Tseng benchmark)

Conclusion  Integral, cost function-driven on-line test synthesis framework  Properties and contributions: Versatility : hardware- or time-redundancy according to designer’s requirements Fully automatic insertion of self-checking resources Quantification of on-line testability Utilisation of the inversion testing idea