Optimization of the Microelectronics Fabrication Lab Process Abstract The laboratory component of the microelectronics fabrication class is an important tool in teaching students the methods used to create microelectronic devices. Recently, a number of problems with the current process were identified. These include a badly scratched photolithography mask set, non-uniformities in the p-type diffusions and difficulties with non-ohmic contacts. The goal of this project is to identify the cause of these problems, devise appropriate corrections, and propose any other changes the group identifies that could enhance the teaching effectiveness of the class. This will be done by designing a new set of photolithography masks, performing experiments, research and simulations to identify causes and solutions to the issues with the diffusions and contacts. At the conclusion of this project, the group will present a new set of photolithography masks and other process improvements. SD May Team Members Client / Advisor Acknowledgements Jerome Helbert EE Ryan McDermott EE Professor Gary Tuttle John Carr Dan Stieler Leah Henze EE Alexander Smith EE Todd Boge Brandon Bohlen Introduction Project Overview Resources and Schedule Problem Statement Problem: Several issues in the current fabrication process cause device failure and therefore detract from the educational experience of the lab. Identified issues include: Badly scratched photolithography mask set Non-uniform Diffusions Non-ohmic Contacts Solutions: Redesign and produce a new mask set Modify process to improve contacts and diffusions Environment, Uses and Users Process and products are specifically designed for use in the NSF lab at Iowa State University Semi-clean environment Climate controlled Process used by faculty and graduate students to teach CMOS fabrication to undergraduate and graduate students Students have little to no experience with fabrication technology Assumptions and Limitations Limitations Time required (for a single lab or entire process) can not change significantly Compatible with current lab equipment Compatible with the CMOS 70 process used in lab Mask completed in L-Edit Version 8.11 Minimum feature size on mask is 4µm Assumptions Lab students are primarily of EE, MatE, IE and Physics backgrounds Lab materials and equipment will not change Class format will not change Mask set will be used for 3 – 4 yrs Project Deliverables New photolithography mask set End user documentation to accompany mask set Updated CMOS 70 Process Including process changes to improve contacts and diffusions Documentation of process changes Design Objectives Create a new mask set, include devices appropriate to the background of the class Modify process to increase device yield Functional Requirements Mask set to support CMOS devices Mask set easy for inexperienced users to use Easy to align with adequate open viewing space Devices more tolerant to misalignments Process improved to produce uniform diffusions Process improved to produce ohmic contacts Constraints New mask layout no larger than 3.81 x 3.81 cm Make use of currently available materials and equipment Not to increase operating budget of class Project Milestones Identify current problem areas Identify and test solutions to problems Create new photolithography mask set Test modified process with new mask set Document all project results Approach Identification of Primary Issues in Current CMOS 70 Process Design and Perform Experiments to Characterize Current Process Selection of Devices for New Mask Set Design New Mask Set Fabrication of Masks (Performed by Dan Stieler) Design and Perform Experiments to Test Potential Solutions Initial Testing of Masks and Process Improvements (Performed by Team) End User Testing (Performed by EE 432 Students) Technologies Considered Mask Design Software Cadence L-Edit Version 8.11 Process Improvements Simulation Programs: SUPREM Technologies: Alternate quartz diffusion boats Alternate source wafers Various metal contacts Conclusions Testing Considerations Initial testing Controlled experiments performed by team Full process run performed by team End User Testing Full process performed by students with proper safety training in the fabrication class. Figure 1 - Undesired shorts due to scratched photolithography mask. Material Costs 50 Silicon Wafers$500 Lab Supplies$1890 Fabrication Mask Fabrication$300 Other Costs Report Binding$10 Poster$30 Total$2,730 Personal Effort Requirements Based upon assignment of project tasks Total: 848 hours Project Costs Based upon projected materials use in experiments Mask fabrication cost given for in-house fabrication Figure 3 – Personal effort requirements for project by team member. Table 1 – Projected Project Costs Figure 5 – Photolithography mask set produced by team. Figure 4 – Project Gantt Chart Figure 2 – Process improvement identified by team. Additional guard wafers in the diffusion boat results in more uniform p- type diffusions. The overall goal of this project was to improve the Microelectronics Fabrication lab in order to increase the overall teaching effectiveness. This will allow students to better understand the CMOS fabrication process which will in turn aid them in future course work or in industry. These improvements can be made through a combination of replacing the existing photolithography mask set and adjusting the current process parameters to increase the overall yield of functioning devices.